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readings [2015/09/17 18:01]
nandita [Optional Readings Mentioned in Lecture]
readings [2015/09/23 15:59]
nandita [Review Set 4]
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   * Evers et al., [[http://​www.ece.cmu.edu/​~ece740/​f10/​lib/​exe/​fetch.php?​media=analysisofcorrelationandpredictability.pdf | An Analysis of Correlation and Predictability:​ What Makes Two-Level Branch Predictors Work]], //ISCA 1998//   * Evers et al., [[http://​www.ece.cmu.edu/​~ece740/​f10/​lib/​exe/​fetch.php?​media=analysisofcorrelationandpredictability.pdf | An Analysis of Correlation and Predictability:​ What Makes Two-Level Branch Predictors Work]], //ISCA 1998//
   * Chang et al., [[http://​ieeexplore.ieee.org/​xpls/​abs_all.jsp?​arnumber=717404 | Branch classification:​ a new mechanism for improving branch predictor performance]],​ //MICRO 1994//   * Chang et al., [[http://​ieeexplore.ieee.org/​xpls/​abs_all.jsp?​arnumber=717404 | Branch classification:​ a new mechanism for improving branch predictor performance]],​ //MICRO 1994//
-  * Sprangle et al., [[http://​ieeexplore.ieee.org/​xpls/​abs_all.jsp?​arnumber=604711The ​Agree Predictor: A Mechanism for Reducing Negative Branch History Interference]],​ //ISCA 1997.//+  * Sprangle et al., [[http://​ieeexplore.ieee.org/​xpls/​abs_all.jsp?​arnumber=604711 | The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference]],​ //ISCA 1997.//
   * Seznec, [[http://​www.irisa.fr/​caps/​oldcaps/​people/​seznec/​Optim2bcgskew.pdf | An optimized 2bcgskew branch predictor]],​ //IRISA Tech Report 1993.//   * Seznec, [[http://​www.irisa.fr/​caps/​oldcaps/​people/​seznec/​Optim2bcgskew.pdf | An optimized 2bcgskew branch predictor]],​ //IRISA Tech Report 1993.//
   * Michaud, [[http://​citeseerx.ist.psu.edu/​viewdoc/​download?​doi=10.1.1.94.63&​rep=rep1&​type=pdf | Trading conflict and capacity aliasing in conditional branch predictors]],​ //ISCA 1997//   * Michaud, [[http://​citeseerx.ist.psu.edu/​viewdoc/​download?​doi=10.1.1.94.63&​rep=rep1&​type=pdf | Trading conflict and capacity aliasing in conditional branch predictors]],​ //ISCA 1997//
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   * Jimenez and Lin, [[https://​www.cs.utexas.edu/​~lin/​papers/​hpca01.pdf | Dynamic Branch Prediction with Perceptrons]],​ //HPCA 2001//   * Jimenez and Lin, [[https://​www.cs.utexas.edu/​~lin/​papers/​hpca01.pdf | Dynamic Branch Prediction with Perceptrons]],​ //HPCA 2001//
   * Rosenblatt, [[http://​catalog.hathitrust.org/​Record/​000203591 | Principles of Neurodynamics:​ Perceptrons and the Theory of Brain Mechanisms]],​ //1962//   * Rosenblatt, [[http://​catalog.hathitrust.org/​Record/​000203591 | Principles of Neurodynamics:​ Perceptrons and the Theory of Brain Mechanisms]],​ //1962//
 +  * Seznec and Michaud, ​ [[http://​www.jilp.org/​vol8/​v8paper1.pdf | A case for (partially) tagged Geometric History Length Branch Prediction]],​ //JILP 2006.//
 +  * Andre Seznec, [[http://​www.jilp.org/​cbp2014/​paper/​AndreSeznec.pdf | TAGE-SC-L branch predictors]],​ //CBP 2014//
 +  * Chappell et al., [[http://​hps.ece.utexas.edu/​pub/​ssmt_isca_29.pdf | Difficult-Path Branch Prediction Using Subordinate Microthreads]],​ //ISCA 2002.//
 +  * Jacobsen et al., [[http://​people.engr.ncsu.edu/​ericro/​publications/​conference_MICRO-29_jrs.pdf | Assigning Confidence to Conditional Branch Predictions]],​ //MICRO 1996.//
 +  * Manne et al., [[http://​www.cs.utah.edu/​~rajeev/​cs7810/​papers/​manne98.pdf | Pipeline Gating: Speculation Control for Energy Reduction]],​ //ISCA 1998//
 +  * Pettis and Hansen, [[http://​perso.ensta-paristech.fr/​~bmonsuez/​Cours/​B6-4/​Articles/​papers15.pdf | Profile Guided Code Positioning]],​ //PLDI 1990.//
 +  * Hwu et al., [[http://​impact.crhc.illinois.edu/​shared/​papers/​hwu_jsuper93.pdf | The Superblock: An effective technique for VLIW and superscalar compilation,​” Journal of Supercomputing]],​ //1993.//
 +  * Rotenberg et al., [[http://​people.engr.ncsu.edu/​ericro/​publications/​conference_MICRO-29_rbs.pdf | Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching]], //MICRO 1996.//
 +  * Patel et al., [[https://​www.eecs.umich.edu/​techreports/​cse/​97/​CSE-TR-335-97.pdf | Critical Issues Regarding the Trace Cache Fetch Mechanism]],​ //Umich TR, 1997.//
 +  * A. Peleg, U. Weiser, [[http://​patft1.uspto.gov/​netacgi/​nph-Parser?​Sect1=PTO1&​Sect2=HITOFF&​d=PALL&​p=1&​u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&​r=1&​f=G&​l=50&​s1=5381533.PN.&​OS=PN/​5381533&​RS=PN/​5381533 | Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line]], //United States Patent No. 5,381,533, Jan 10, 1995.// ​
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 +
 +
 +===== Recitation 4 =====
 +
 +==== Review Set 4 ====
 +  * Eiman Ebrahimi et. al., [[ https://​users.ece.cmu.edu/​~omutlu/​pub/​fst_asplos10.pdf | Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], ​  //​ ASPLOS 2010// **[[Review Required]]**
 +  * Rachata Ausavarungnirun et. al., [[http://​users.ece.cmu.edu/​~omutlu/​pub/​MeDiC-for-GPGPUs_pact15.pdf | Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance]], ​ //PACT 2015// **[[Review Required]]**
 +  * 
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 +