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readings [2015/09/16 04:20] nandita [Optional Readings Mentioned in Lecture] |
readings [2015/09/17 17:48] nandita [Optional Readings Mentioned in Lecture] |
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| * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.// | * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.// | ||
| * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// | * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// | ||
| + | * Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// | ||
| + | * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// | ||
| + | * Dennis et al.,[[https://courses.cs.washington.edu/courses/cse548/11au/Dennis-Dataflow.pdf | A Preliminary Architecture for a Basic Data Flow Processor]], //ISCA 1974.// | ||
| + | |||
| + | ===== Lecture 5 ===== | ||
| + | ==== Optional Readings Mentioned in Lecture ==== | ||
| + | |||
| + | * T. Yeh and Y. Patt [[http://web.cecs.pdx.edu/~herb/ece587s15/Papers/08_yeh_patt_br_predict_1991.pdf | Two-Level Adaptive Training Branch Prediction]], //Intl. Symposium on Microarchitecture, November 1991. MICRO Test of Time Award Winner (after 24 years).// | ||
| + | * Kessler, R. E., [[http://cseweb.ucsd.edu/classes/sp00/cse241/alpha.pdf | The Alpha 21264 Microprocessor]], //IEEE Micro, March/April 1999, pp. 24-36 // | ||
| + | * McFarling, S., [[http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-36.pdf | Combining Branch Predictors]], //DEC WRL Technical Report, TN-36, June 1993// | ||
| + | * Smith and Sohi, [[ftp://ftp.cs.wisc.edu/sohi/papers/1995/ieee-proc.superscalar.pdf | The Microarchitecture of Superscalar Processors]], //Proceedings of the IEEE, 1995.// | ||
| + | * Evers et al., [[http://www.ece.cmu.edu/~ece740/f10/lib/exe/fetch.php?media=analysisofcorrelationandpredictability.pdf | An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work]], //ISCA 1998// | ||