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readings [2015/09/16 04:00] nandita [Review Set 3 (due 3 PM)] |
readings [2015/09/16 04:00] nandita [Review Set 3 (due 3 PM)] |
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| - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]** | - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]** | ||
| - Joao et al., [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications]], //ASPLOS 2012.// **[Review Required]** | - Joao et al., [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications]], //ASPLOS 2012.// **[Review Required]** | ||
| - | - Ebrahimi et al., [[ http://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf| Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], //ASPLOS 2010.// **[Review Required]** | + | - Ebrahimi et al., [[ http://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf| Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], //ASPLOS 2010.// **[Optional]** |
| ==== Optional Readings Mentioned in Lecture ==== | ==== Optional Readings Mentioned in Lecture ==== | ||