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readings [2015/09/13 21:39] nandita [Review Set 2 due (3 PM)] |
readings [2015/09/17 17:38] nandita [Optional Readings Mentioned in Lecture] |
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===== Recitation 1 ===== | ===== Recitation 1 ===== | ||
- | ==== Review Set 1 due (3 PM)==== | + | ==== Review Set 1 (due 3 PM)==== |
- Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | - Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | ||
Systems]], //Invited Article in Supercomputing Frontiers and Innovations | Systems]], //Invited Article in Supercomputing Frontiers and Innovations | ||
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===== Recitation 2 ===== | ===== Recitation 2 ===== | ||
- | ==== Review Set 2 due (3 PM)==== | + | ==== Review Set 2 (due 3 PM)==== |
- Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// **[Review Required]** | - Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// **[Review Required]** | ||
- Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]** | - Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]** | ||
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+ | ===== Recitation 3 ===== | ||
+ | ==== Review Set 3 (due 3 PM) ==== | ||
+ | - Cai et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Review Required]** | ||
+ | - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]** | ||
+ | - Joao et al., [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications]], //ASPLOS 2012.// **[Review Required]** | ||
+ | - Ebrahimi et al., [[ http://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf| Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], //ASPLOS 2010.// **[Optional]** | ||
+ | ==== Optional Readings Mentioned in Lecture ==== | ||
+ | * Cai et al., [[ https://users.ece.cmu.edu/~omutlu/pub/flash-memory-data-retention_hpca15.pdf | Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery]], //HPCA 2015// | ||
+ | * Lee et al., [[http://www.cs.rochester.edu/~ipek/ieeemicro10.pdf | Phase Change Technology and the Future of Main Memory]], //IEEE Micro 2010// | ||
+ | * Suleman et al., [[http://users.ece.cmu.edu/~omutlu/pub/acs_asplos09.pdf | Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures]], //ASPLOS 2009// | ||
+ | * Kang et al., [[http://users.ece.cmu.edu/~yoonguk/papers/kang-memoryforum14.pdf | Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling]], //Memory Form 2014// | ||
+ | * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.// | ||
+ | * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// | ||
+ | * Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// | ||
+ | * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// | ||
+ | * Dennis et al.,[[https://courses.cs.washington.edu/courses/cse548/11au/Dennis-Dataflow.pdf | A Preliminary Architecture for a Basic Data Flow Processor]], //ISCA 1974.// | ||
+ | |||
+ | ===== Lecture 5 ===== | ||
+ | ==== Optional Readings Mentioned in Lecture ==== |