Differences

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--- readings [2015/09/13 21:36]
nandita [Review Set 2 due (3 PM)]
+++ readings [2015/09/16 03:48]
nandita [Optional Readings Mentioned in Lecture]
@@ Line 12: / Line 12: @@
 Austin, TX, September 2014//** [Review Required]**
   - Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for
-Parallel Graph Processing]], //Proceedings of the 42nd International Symposium on
+Parallel Graph Processing]], //ISCA 2015.// ** [Optional]**
-Computer Architecture (ISCA), Portland, OR, June 2015.// ** [Optional]**
   - Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//** [Review Required]**
@@ Line 26: / Line 25: @@
 ==== Review Set 2 due (3 PM)====
-  -  Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]],  ISCA 2015. **[Review Required]**
+  -  Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]],  //ISCA 2015.// **[Review Required]**
   -  Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]**
   -  Jeffrey D. Ullman, [[http://cacm.acm.org/magazines/2015/9/191183-experiments-as-research-validation/fulltext | Experiments as Research Validation: Have We Gone Too Far?]], CACM 2015. **[Review Required]**
-  -  Nandita Vijaykumar, Gennady Pekhimenko, Adwait Jog, Abhishek Bhowmick, Rachata Ausavarungnirun, Chita Das, Mahmut Kandemir, Todd C. Mowry, and Onur Mutlu, [[https://users.ece.cmu.edu/~omutlu/pub/caba-gpu-assist-warps_isca15.pdf | A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps]], Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015. **[Review Required]**
+  -  Nandita Vijaykumar et al., [[https://users.ece.cmu.edu/~omutlu/pub/caba-gpu-assist-warps_isca15.pdf | A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps]],  //ISCA 2015.// **[Review Required]**
-  - Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch, Ken Mai, and Onur Mutlu, [[https://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], Proceedings of the 45th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), Rio de Janeiro, Brazil, June 2015. **[Optional]**
+  - Yu Cai et al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Optional]**
 ==== Optional Readings Mentioned in Lecture ====
   - Moore, [[http://www.cs.utexas.edu/~fussell/courses/cs352h/papers/moore.pdf | Cramming more components onto integrated circuits]], Electronics Magazine, 1965.
@@ Line 50: / Line 49: @@
   - Larus, [[http://research.microsoft.com/pubs/70581/tr-2008-69.pdf | Spending Moore's Dividend]]
+===== Recitation 3 =====
+==== Review Set 3 (due 3 PM) ====
+==== Optional Readings Mentioned in Lecture ====