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readings [2015/09/13 21:36] nandita [Review Set 2 due (3 PM)] |
readings [2015/09/13 21:37] nandita [Review Set 1 due (3 PM)] |
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| Austin, TX, September 2014//** [Review Required]** | Austin, TX, September 2014//** [Review Required]** | ||
| - Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | - Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | ||
| - | Parallel Graph Processing]], //Proceedings of the 42nd International Symposium on | + | Parallel Graph Processing]], //ISCA 2015.// ** [Optional]** |
| - | Computer Architecture (ISCA), Portland, OR, June 2015.// ** [Optional]** | + | |
| - Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//** [Review Required]** | - Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//** [Review Required]** | ||