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readings [2015/09/09 05:27] nandita [Optional Readings Mentioned in Lecture] |
readings [2015/09/16 04:00] nandita [Review Set 3 (due 3 PM)] |
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===== Recitation 1 ===== | ===== Recitation 1 ===== | ||
- | ==== Review Set 1 due (3 PM)==== | + | ==== Review Set 1 (due 3 PM)==== |
- Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | - Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | ||
Systems]], //Invited Article in Supercomputing Frontiers and Innovations | Systems]], //Invited Article in Supercomputing Frontiers and Innovations | ||
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Austin, TX, September 2014//** [Review Required]** | Austin, TX, September 2014//** [Review Required]** | ||
- Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | - Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | ||
- | Parallel Graph Processing]], //Proceedings of the 42nd International Symposium on | + | Parallel Graph Processing]], //ISCA 2015.// ** [Optional]** |
- | Computer Architecture (ISCA), Portland, OR, June 2015.// ** [Optional]** | + | |
- Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//** [Review Required]** | - Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//** [Review Required]** | ||
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===== Recitation 2 ===== | ===== Recitation 2 ===== | ||
- | ==== Review Set 2 due (3 PM)==== | + | ==== Review Set 2 (due 3 PM)==== |
- | - Junwhan Ahn, Sungpack Hong, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], Proceedings of the 42nd International Symposium on Computer Architecture(ISCA), Portland, OR, June 2015. **[Review Required]** | + | - Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// **[Review Required]** |
- Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]** | - Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]** | ||
- Jeffrey D. Ullman, [[http://cacm.acm.org/magazines/2015/9/191183-experiments-as-research-validation/fulltext | Experiments as Research Validation: Have We Gone Too Far?]], CACM 2015. **[Review Required]** | - Jeffrey D. Ullman, [[http://cacm.acm.org/magazines/2015/9/191183-experiments-as-research-validation/fulltext | Experiments as Research Validation: Have We Gone Too Far?]], CACM 2015. **[Review Required]** | ||
- | - Nandita Vijaykumar, Gennady Pekhimenko, Adwait Jog, Abhishek Bhowmick, Rachata Ausavarungnirun, Chita Das, Mahmut Kandemir, Todd C. Mowry, and Onur Mutlu, [[https://users.ece.cmu.edu/~omutlu/pub/caba-gpu-assist-warps_isca15.pdf | A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps]], Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015. **[Review Required]** | + | - Nandita Vijaykumar et al., [[https://users.ece.cmu.edu/~omutlu/pub/caba-gpu-assist-warps_isca15.pdf | A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps]], //ISCA 2015.// **[Review Required]** |
+ | - Yu Cai et al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Optional]** | ||
==== Optional Readings Mentioned in Lecture ==== | ==== Optional Readings Mentioned in Lecture ==== | ||
- Moore, [[http://www.cs.utexas.edu/~fussell/courses/cs352h/papers/moore.pdf | Cramming more components onto integrated circuits]], Electronics Magazine, 1965. | - Moore, [[http://www.cs.utexas.edu/~fussell/courses/cs352h/papers/moore.pdf | Cramming more components onto integrated circuits]], Electronics Magazine, 1965. | ||
- Kuhn, [[http://www.amazon.com/gp/aw/d/B007USH7J2/ref=tmm_kin_title_0?ie=UTF8&qid=&sr= | The structure of scientific revolutions]], 1962. | - Kuhn, [[http://www.amazon.com/gp/aw/d/B007USH7J2/ref=tmm_kin_title_0?ie=UTF8&qid=&sr= | The structure of scientific revolutions]], 1962. | ||
- | - {{http://www.cs.utexas.edu/users/mckinley/notes/reviewing.html|Hill and McKinley, "Notes on Constructive and Positive Reviewing".}} | + | - Hill and McKinley, [[http://www.cs.utexas.edu/users/mckinley/notes/reviewing.html| Notes on Constructive and Positive Reviewing]] |
- | - {{writing-papers.pdf|Levin and Redell, "How (and how not) to write a good systems paper," OSR 1983.}} | + | - Levin and Redell, [[writing-papers.pdf | How (and how not) to write a good systems paper]], OSR 1983. |
- | - {{http://research.microsoft.com/en-us/um/people/simonpj/papers/giving-a-talk/writing-a-paper-slides.pdf|Jones, "How to Write a Great Research Paper".}} | + | - Jones, [[http://research.microsoft.com/en-us/um/people/simonpj/papers/giving-a-talk/writing-a-paper-slides.pdf|How to Write a Great Research Paper]] |
+ | - Fong, [[rmeta_fong.pdf|How to Write a CS Research Paper: A Bibliography]] | ||
+ | - Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, [[ https://users.ece.cmu.edu/~omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture]], Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015. | ||
+ | - Nickolls and Dally, [[http://sbel.wisc.edu/Courses/ME964/Literature/onGPUcomputingDally2010.pdf | The GPU Computing Era]] , IEEE Micro 2010. | ||
+ | - Schulte et al., [[http://dx.doi.org/10.1109/MM.2015.71 | Achieving Exascale Capabilities through Heterogeneous Computing]] , IEEE Micro 2015. | ||
+ | - Michael Mitzenmacher, [[http://cacm.acm.org/magazines/2015/9/191184-theory-without-experiments/fulltext| Theory Without Experiments: Have We Gone Too Far?]], CACM 2015. | ||
+ | - Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], ISCA 2014. | ||
+ | - Meza et al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], IEEE Comp. Arch. Letters, 2012. | ||
+ | - Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], ICCD 2012. | ||
+ | - Subramanian et al., [[https://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf | MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,]], HPCA 2013 | ||
+ | - Lui et al., [[http://research.microsoft.com/pubs/147610/asplos_2011.pdf | Flikker: Saving DRAM Refresh-power through Critical Data Partitioning]], ASPLOS 2011. | ||
+ | - Lefurgy, et al., [[http://dl.acm.org/citation.cfm?id=957972 | Energy Management for Commercial Servers]], IEEE Computer 2003. | ||
+ | - Larus, [[http://research.microsoft.com/pubs/70581/tr-2008-69.pdf | Spending Moore's Dividend]] | ||
+ | |||
+ | |||
+ | ===== Recitation 3 ===== | ||
+ | ==== Review Set 3 (due 3 PM) ==== | ||
+ | - Cai et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Review Required]** | ||
+ | - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]** | ||
+ | - Joao et al., [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications]], //ASPLOS 2012.// **[Review Required]** | ||
+ | - Ebrahimi et al., [[ http://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf| Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], //ASPLOS 2010.// **[Review Required]** | ||
+ | ==== Optional Readings Mentioned in Lecture ==== |