This shows you the differences between two versions of the page.
Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
readings [2015/09/05 18:43] nandita [Recitation 1] |
readings [2015/09/29 05:44] nandita [Optional Readings Mentioned in the Lecture] |
||
---|---|---|---|
Line 4: | Line 4: | ||
===== Recitation 1 ===== | ===== Recitation 1 ===== | ||
+ | ==== Review Set 1==== | ||
- Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | - Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | ||
Systems]], //Invited Article in Supercomputing Frontiers and Innovations | Systems]], //Invited Article in Supercomputing Frontiers and Innovations | ||
Line 11: | Line 12: | ||
Austin, TX, September 2014//** [Review Required]** | Austin, TX, September 2014//** [Review Required]** | ||
- Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | - Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | ||
- | Parallel Graph Processing]], //Proceedings of the 42nd International Symposium on | + | Parallel Graph Processing]], //ISCA 2015.// ** [Optional]** |
- | Computer Architecture (ISCA), Portland, OR, June 2015.// | + | |
- Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//** [Review Required]** | - Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//** [Review Required]** | ||
+ | |||
+ | ==== Optional Readings Mentioned in Lecture ==== | ||
+ | - Smith, [[http://www.cs.utexas.edu/users/mckinley/notes/reviewing-smith.pdf | Task of the Referee]],// IEEE Computer 1990//. | ||
+ | - Hill and McKinley, [[http://www.cs.utexas.edu/users/mckinley/notes/reviewing.html|Notes on Constructive and Positive Reviewing]] | ||
+ | - Thomas Moscibroda and Onur Mutlu, [[http://users.ece.cmu.edu/~omutlu/pub/mph_usenix_security07.pdf | Memory Performance Attacks: Denial of Memory Service | ||
+ | in Multi-Core Systems]], //Proceedings of the 16th USENIX Security Symposium (USENIX SECURITY), | ||
+ | pages 257-274, Boston, MA, August 2007.// | ||
+ | |||
+ | ===== Recitation 2 ===== | ||
+ | |||
+ | ==== Review Set 2==== | ||
+ | - Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// **[Review Required]** | ||
+ | - Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco, [[ http://www.cs.nyu.edu/courses/spring12/CSCI-GA.3033-012/ieee-micro-echelon.pdf | GPUs and the Future of Parallel Computing]], IEEE Micro 2011. **[Review Required]** | ||
+ | - Jeffrey D. Ullman, [[http://cacm.acm.org/magazines/2015/9/191183-experiments-as-research-validation/fulltext | Experiments as Research Validation: Have We Gone Too Far?]], CACM 2015. **[Review Required]** | ||
+ | - Nandita Vijaykumar et al., [[https://users.ece.cmu.edu/~omutlu/pub/caba-gpu-assist-warps_isca15.pdf | A Case for Core-Assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps]], //ISCA 2015.// **[Review Required]** | ||
+ | - Yu Cai et al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Optional]** | ||
+ | ==== Optional Readings Mentioned in Lecture ==== | ||
+ | - Moore, [[http://www.cs.utexas.edu/~fussell/courses/cs352h/papers/moore.pdf | Cramming more components onto integrated circuits]], Electronics Magazine, 1965. | ||
+ | - Kuhn, [[http://www.amazon.com/gp/aw/d/B007USH7J2/ref=tmm_kin_title_0?ie=UTF8&qid=&sr= | The structure of scientific revolutions]], 1962. | ||
+ | - Hill and McKinley, [[http://www.cs.utexas.edu/users/mckinley/notes/reviewing.html| Notes on Constructive and Positive Reviewing]] | ||
+ | - Levin and Redell, [[writing-papers.pdf | How (and how not) to write a good systems paper]], OSR 1983. | ||
+ | - Jones, [[http://research.microsoft.com/en-us/um/people/simonpj/papers/giving-a-talk/writing-a-paper-slides.pdf|How to Write a Great Research Paper]] | ||
+ | - Fong, [[rmeta_fong.pdf|How to Write a CS Research Paper: A Bibliography]] | ||
+ | - Junwhan Ahn, Sungjoo Yoo, Onur Mutlu, and Kiyoung Choi, [[ https://users.ece.cmu.edu/~omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture]], Proceedings of the 42nd International Symposium on Computer Architecture (ISCA), Portland, OR, June 2015. | ||
+ | - Nickolls and Dally, [[http://sbel.wisc.edu/Courses/ME964/Literature/onGPUcomputingDally2010.pdf | The GPU Computing Era]] , IEEE Micro 2010. | ||
+ | - Schulte et al., [[http://dx.doi.org/10.1109/MM.2015.71 | Achieving Exascale Capabilities through Heterogeneous Computing]] , IEEE Micro 2015. | ||
+ | - Michael Mitzenmacher, [[http://cacm.acm.org/magazines/2015/9/191184-theory-without-experiments/fulltext| Theory Without Experiments: Have We Gone Too Far?]], CACM 2015. | ||
+ | - Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], ISCA 2014. | ||
+ | - Meza et al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], IEEE Comp. Arch. Letters, 2012. | ||
+ | - Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], ICCD 2012. | ||
+ | - Subramanian et al., [[https://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf | MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,]], HPCA 2013 | ||
+ | - Lui et al., [[http://research.microsoft.com/pubs/147610/asplos_2011.pdf | Flikker: Saving DRAM Refresh-power through Critical Data Partitioning]], ASPLOS 2011. | ||
+ | - Lefurgy, et al., [[http://dl.acm.org/citation.cfm?id=957972 | Energy Management for Commercial Servers]], IEEE Computer 2003. | ||
+ | - Larus, [[http://research.microsoft.com/pubs/70581/tr-2008-69.pdf | Spending Moore's Dividend]] | ||
+ | |||
+ | |||
+ | ===== Recitation 3 ===== | ||
+ | ==== Review Set 3 ==== | ||
+ | - Cai et al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-read-disturb-errors_dsn15.pdf | Read Disturb Errors in MLC NAND Flash Memory: Characterization and Mitigation]], //DSN 2015.// **[Review Required]** | ||
+ | - Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// **[Review Required]** | ||
+ | - Joao et al., [[http://users.ece.cmu.edu/~omutlu/pub/bottleneck-identification-and-scheduling_asplos12.pdf | Bottleneck Identification and Scheduling in Multithreaded Applications]], //ASPLOS 2012.// **[Review Required]** | ||
+ | - Ebrahimi et al., [[ http://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf| Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], //ASPLOS 2010.// **[Optional]** | ||
+ | ==== Optional Readings Mentioned in Lecture ==== | ||
+ | * Cai et al., [[ https://users.ece.cmu.edu/~omutlu/pub/flash-memory-data-retention_hpca15.pdf | Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery]], //HPCA 2015// | ||
+ | * Lee et al., [[http://www.cs.rochester.edu/~ipek/ieeemicro10.pdf | Phase Change Technology and the Future of Main Memory]], //IEEE Micro 2010// | ||
+ | * Suleman et al., [[http://users.ece.cmu.edu/~omutlu/pub/acs_asplos09.pdf | Accelerating Critical Section Execution with Asymmetric Multi-Core Architectures]], //ASPLOS 2009// | ||
+ | * Kang et al., [[http://users.ece.cmu.edu/~yoonguk/papers/kang-memoryforum14.pdf | Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling]], //Memory Form 2014// | ||
+ | * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.// | ||
+ | * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// | ||
+ | * Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for Parallel Graph Processing]], //ISCA 2015.// | ||
+ | * Loh et al., [[http://ag-rs-www.informatik.uni-kl.de/publications/data/Loh08.pdf| 3D-Stacked Memory Architectures for Multi-Core Processors]], //ISCA 2008.// | ||
+ | * Dennis et al.,[[https://courses.cs.washington.edu/courses/cse548/11au/Dennis-Dataflow.pdf | A Preliminary Architecture for a Basic Data Flow Processor]], //ISCA 1974.// | ||
+ | |||
+ | ===== Lecture 5 ===== | ||
+ | ==== Optional Readings Mentioned in Lecture ==== | ||
+ | |||
+ | * T. Yeh and Y. Patt [[http://web.cecs.pdx.edu/~herb/ece587s15/Papers/08_yeh_patt_br_predict_1991.pdf | Two-Level Adaptive Training Branch Prediction]], //Intl. Symposium on Microarchitecture, November 1991. MICRO Test of Time Award Winner (after 24 years).// | ||
+ | * Kessler, R. E., [[http://cseweb.ucsd.edu/classes/sp00/cse241/alpha.pdf | The Alpha 21264 Microprocessor]], //IEEE Micro, March/April 1999, pp. 24-36 // | ||
+ | * McFarling, S., [[http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-36.pdf | Combining Branch Predictors]], //DEC WRL Technical Report, TN-36, June 1993// | ||
+ | * Smith and Sohi, [[ftp://ftp.cs.wisc.edu/sohi/papers/1995/ieee-proc.superscalar.pdf | The Microarchitecture of Superscalar Processors]], //Proceedings of the IEEE, 1995.// | ||
+ | * Evers et al., [[http://www.ece.cmu.edu/~ece740/f10/lib/exe/fetch.php?media=analysisofcorrelationandpredictability.pdf | An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work]], //ISCA 1998// | ||
+ | * Chang et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=717404 | Branch classification: a new mechanism for improving branch predictor performance]], //MICRO 1994// | ||
+ | * Sprangle et al., [[http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=604711 | The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference]], //ISCA 1997.// | ||
+ | * Seznec, [[http://www.irisa.fr/caps/oldcaps/people/seznec/Optim2bcgskew.pdf | An optimized 2bcgskew branch predictor]], //IRISA Tech Report 1993.// | ||
+ | * Michaud, [[http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.94.63&rep=rep1&type=pdf | Trading conflict and capacity aliasing in conditional branch predictors]], //ISCA 1997// | ||
+ | * Lee et al., [[http://www-inst.eecs.berkeley.edu/~cs152/sp05/handouts/p4-lee.pdf | The bi-mode branch predictor]], //MICRO 1997.// | ||
+ | * Eden and Mudge, [[http://web.eecs.umich.edu/~tnm/papers/yags.pdf | The YAGS branch prediction scheme]], //MICRO 1998.// | ||
+ | * Seznec et al., [[http://www.cs.utah.edu/~rajeev/cs7810/papers/seznec02.pdf | Design tradeoffs for the Alpha EV8 conditional branch predictor]], //ISCA 2002.// | ||
+ | * Chappell et al., [[http://www.ece.cmu.edu/~ece740/f13/lib/exe/fetch.php?media=chappell_ssmt99.pdf | Simultaneous Subordinate Microthreading (SSMT)]], //ISCA 1999.// | ||
+ | * Seznec, [[https://classes.soe.ucsc.edu/cmpe221/Spring06/papers/03trace.pdf | Analysis of the O-Geometric History Length branch predictor]], //ISCA 2005// | ||
+ | * Gochman et al., [[http://www.weblearn.hs-bremen.de/risse/RST/WS04/Centrino/vol7iss2_art03.pdf | The Intel Pentium M Processor: Microarchitecture and Performance]], //Intel Technology Journal, May 2003// | ||
+ | * Jimenez and Lin, [[https://www.cs.utexas.edu/~lin/papers/hpca01.pdf | Dynamic Branch Prediction with Perceptrons]], //HPCA 2001// | ||
+ | * Rosenblatt, [[http://catalog.hathitrust.org/Record/000203591 | Principles of Neurodynamics: Perceptrons and the Theory of Brain Mechanisms]], //1962// | ||
+ | * Seznec and Michaud, [[http://www.jilp.org/vol8/v8paper1.pdf | A case for (partially) tagged Geometric History Length Branch Prediction]], //JILP 2006.// | ||
+ | * Andre Seznec, [[http://www.jilp.org/cbp2014/paper/AndreSeznec.pdf | TAGE-SC-L branch predictors]], //CBP 2014// | ||
+ | * Chappell et al., [[http://hps.ece.utexas.edu/pub/ssmt_isca_29.pdf | Difficult-Path Branch Prediction Using Subordinate Microthreads]], //ISCA 2002.// | ||
+ | * Jacobsen et al., [[http://people.engr.ncsu.edu/ericro/publications/conference_MICRO-29_jrs.pdf | Assigning Confidence to Conditional Branch Predictions]], //MICRO 1996.// | ||
+ | * Manne et al., [[http://www.cs.utah.edu/~rajeev/cs7810/papers/manne98.pdf | Pipeline Gating: Speculation Control for Energy Reduction]], //ISCA 1998// | ||
+ | * Pettis and Hansen, [[http://perso.ensta-paristech.fr/~bmonsuez/Cours/B6-4/Articles/papers15.pdf | Profile Guided Code Positioning]], //PLDI 1990.// | ||
+ | * Hwu et al., [[http://impact.crhc.illinois.edu/shared/papers/hwu_jsuper93.pdf | The Superblock: An effective technique for VLIW and superscalar compilation,” Journal of Supercomputing]], //1993.// | ||
+ | * Rotenberg et al., [[http://people.engr.ncsu.edu/ericro/publications/conference_MICRO-29_rbs.pdf | Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching]], //MICRO 1996.// | ||
+ | * Patel et al., [[https://www.eecs.umich.edu/techreports/cse/97/CSE-TR-335-97.pdf | Critical Issues Regarding the Trace Cache Fetch Mechanism]], //Umich TR, 1997.// | ||
+ | * A. Peleg, U. Weiser, [[http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=5381533.PN.&OS=PN/5381533&RS=PN/5381533 | Dynamic Flow Instruction Cache Memory Organized Around Trace Segments Independent of Virtual Address Line]], //United States Patent No. 5,381,533, Jan 10, 1995.// | ||
+ | |||
+ | |||
+ | |||
+ | ===== Recitation 4 ===== | ||
+ | |||
+ | ==== Review Set 4 ==== | ||
+ | * Eiman Ebrahimi et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/fst_asplos10.pdf | Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems]], //ASPLOS 2010// **[Review Required]** | ||
+ | * Rachata Ausavarungnirun et. al., [[http://users.ece.cmu.edu/~omutlu/pub/MeDiC-for-GPGPUs_pact15.pdf | Exploiting Inter-Warp Heterogeneity to Improve GPGPU Performance]], //PACT 2015// **[Review Required]** | ||
+ | * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013// **[Review Required]** | ||
+ | * Justin Meza et. al., [[ http://users.ece.cmu.edu/~omutlu/pub/flash-memory-failures-in-the-field-at-facebook_sigmetrics15.pdf | A Large-Scale Study of Flash Memory Errors in the Field]], //SIGMETRICS 2015// **[Optional]** | ||
+ | |||
+ | ==== Optional Readings Mentioned in the Lecture ==== | ||
+ | * Kevin Chang et. al., [[ http://www.pdl.cmu.edu/ftp/associated/sbacpad2012_hat.pdf | HAT: Heterogeneous Adaptive Throttling for On-Chip Networks]], //SBAC-PAD 2012// | ||
+ | * Wilson W. L. Fung et. al., [[ https://www.ece.ubc.ca/~aamodt/papers/wwlfung.micro2007.pdf | Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow]], //MICRO 2007// | ||
+ | * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015// | ||
+ | * Justin Meza et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/memory-errors-at-facebook_dsn15.pdf | Revisiting Memory Errors in Large-Scale Production Data Centers: Analysis and Modeling of New Trends from the Field]], //DSN 2015// | ||
+ | * Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | ||
+ | Parallel Graph Processing]], //ISCA 2015.// | ||
+ | * Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.// | ||
+ | * Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization ]], //MICRO 2013// | ||
+ | * Junwhan Ahn et. al., [[ https://users.ece.cmu.edu/~omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf | PIM-Enabled Instructions: A Low-Overhead, Locality-Aware Processing-in-Memory Architecture]], //ISCA 2015.// | ||
+ | * Liu et. al., [[http://www.pdl.cmu.edu/PDL-FTP/NVM/dram-retention_isca13.pdf | An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms]], //ISCA 2013.// | ||
+ | * Khan et. al., [[https://users.ece.cmu.edu/~omutlu/pub/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf | The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study]], //SIGMETRICS 2014.// | ||
+ | * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014// | ||
+ | * Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], ISCA 2014. | ||
+ | * Cai et. al. [[http://www.istc-cc.cmu.edu/publications/papers/2013/flash-programming-interference_iccd13.pdf | Program Interference in MLC NAND Flash Memory: Characterization, Modeling, and Mitigation]]. //ICCD 2013// | ||
+ | * Cai et. al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-error-analysis-and-management_itj13.pdf | Error Analysis and Retention-Aware Error Management for NAND Flash Memory]], //Intel Technology Journal 2013// | ||
+ | * Cai et. al., [[https://users.ece.cmu.edu/~omutlu/pub/neighbor-assisted-error-correction-in-flash_sigmetrics14.pdf | Neighbor-Cell Assisted Error Correction for MLC NAND Flash Memories]], //SIGMETRICS 2014// | ||
+ | * Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015// | ||
+ | * Qureshi et al. [[ https://users.ece.cmu.edu/~omutlu/pub/avatar-dram-refresh_dsn15.pdf | AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems]], //DSN 2015// | ||
+ | * Lee et al., [[ http://users.ece.cmu.edu/~omutlu/pub/pcm_isca09.pdf | Architecting Phase Change Memory as a Scalable DRAM Alternative]], //ISCA 2009// | ||
+ | * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012// | ||
+ | * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012// | ||
+ | |||
+ | ==== Papers Mentioned in the Lecture (Not in Slides) ==== | ||
+ | * Yoon et. al., [[http://users.ece.utexas.edu/~merez/vecc_asplos_2010.pdf | Virtualized and Flexible ECC for Main Memory]], //ASPLOS 2010// | ||
+ | * Cai et al., [[https://users.ece.cmu.edu/~omutlu/pub/flash-memory-data-retention_hpca15.pdf | Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery]], //HPCA 2015// | ||
+ | * Raoux et. al., [[ http://researcher.watson.ibm.com/researcher/files/us-gwburr/PCM_IBMJRD.pdf | Phase-change random access memory: A scalable technology]], //IBM JRD 2008// | ||
+ | * Qureshi et. al., [[http://www.cs.ucsb.edu/~chong/290N-W10/pcm.pdf | Scalable High Performance Main Memory System Using Phase-Change Memory Technology]], //ISCA 2009// | ||
+ | |||
+ | ===== Lecture 5 ===== | ||
+ | ==== Optional Readings Mentioned in the Lecture ==== | ||
+ | * Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | ||
+ | Systems]], //Invited Article in Supercomputing Frontiers and Innovations | ||
+ | (SUPERFRI), 2015.// | ||
+ | * Lee et al., [[http://www.cs.rochester.edu/~ipek/ieeemicro10.pdf | Phase Change Technology and the Future of Main Memory]], //IEEE Micro 2010// | ||
+ | * Yoongu Kim et. al. [[https://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf | Ramulator: A Fast and Extensible DRAM Simulator]], //IEEE Computer Architecture Letters, May 2015.// | ||
+ | * Yoongu Kim et al., [[ http://users.ece.cmu.edu/~omutlu/pub/dram-row-hammer_isca14.pdf| Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors]], //ISCA 2014.// | ||
+ | * Seaborn et.al., [[https://www.blackhat.com/docs/us-15/materials/us-15-Seaborn-Exploiting-The-DRAM-Rowhammer-Bug-To-Gain-Kernel-Privileges.pdf | Exploiting the DRAM rowhammer bug to gain kernel privileges]], //2015// | ||
+ | * Donghyuk Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/tldram_hpca13.pdf | Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture]], //HPCA 2013// | ||
+ | * Liu et al., [[http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf | RAIDR: Retention-Aware Intelligent DRAM Refresh]],// ISCA 2012.// | ||
+ | * Liu et. al., [[http://www.pdl.cmu.edu/PDL-FTP/NVM/dram-retention_isca13.pdf | An Experimental Study of Data Retention Behavior in Modern DRAM Devices: Implications for Retention Time Profiling Mechanisms]], //ISCA 2013.// | ||
+ | * Khan et. al., [[https://users.ece.cmu.edu/~omutlu/pub/error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf | The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study]], //SIGMETRICS 2014.// | ||
+ | * Lee et. al., [[https://users.ece.cmu.edu/~omutlu/pub/adaptive-latency-dram_hpca15.pdf | Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case]], //HPCA 2015// | ||
+ | * Qureshi et al. [[ https://users.ece.cmu.edu/~omutlu/pub/avatar-dram-refresh_dsn15.pdf | AVATAR: A Variable-Retention-Time (VRT) Aware Refresh for DRAM Systems]], //DSN 2015// | ||
+ | * Yoon, Meza et al., [[https://users.ece.cmu.edu/~omutlu/pub/rowbuffer-aware-caching_iccd12.pdf | Row Buffer Locality Aware Caching Policies for Hybrid Memories]], //ICCD 2012// | ||
+ | * Meza et. al., [[https://www.ece.cmu.edu/~safari/pubs/timber_cal12.pdf | Enabling Efficient and Scalable Hybrid Memories]], //IEEE Comp. Arch. Letters, 2012// | ||
+ | * Luo et. al., [[http://users.ece.cmu.edu/~omutlu/pub/heterogeneous-reliability-memory-for-data-centers_dsn14.pdf | Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost]], //DSN 2014// | ||
+ | * Subramanian et al., [[The Application Slowdown Model]], //MICRO 2015.// | ||
+ | * Subramanian et al., [[https://users.ece.cmu.edu/~omutlu/pub/mise-predictable_memory_performance-hpca13.pdf | MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems,]], HPCA 2013 | ||
+ |