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readings [2015/09/05 18:40] nandita |
readings [2015/09/05 19:36] nandita [Optional Readings Mentioned in Lecture] |
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| ===== Recitation 1 ===== | ===== Recitation 1 ===== | ||
| + | ==== Review Set 1 due (3 PM)==== | ||
| - Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | - Onur Mutlu and Lavanya Subramanian, [[http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf | Research Problems and Opportunities in Memory | ||
| Systems]], //Invited Article in Supercomputing Frontiers and Innovations | Systems]], //Invited Article in Supercomputing Frontiers and Innovations | ||
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| - Onur Mutlu, [[http://users.ece.cmu.edu/~omutlu/pub/mutlu_yale75_visions2014_talk.pdf | Rethinking the Systems We Design]], //Technical talk at A Computer Architecture Workshop: | - Onur Mutlu, [[http://users.ece.cmu.edu/~omutlu/pub/mutlu_yale75_visions2014_talk.pdf | Rethinking the Systems We Design]], //Technical talk at A Computer Architecture Workshop: | ||
| Visions for the Future (Celebrating Yale@75) (YALE@75), | Visions for the Future (Celebrating Yale@75) (YALE@75), | ||
| - | Austin, TX, September 2014// | + | Austin, TX, September 2014//** [Review Required]** |
| - Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | - Junwhan Ahn et al., [[ http://users.ece.cmu.edu/~omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf | A Scalable Processing-in-Memory Accelerator for | ||
| Parallel Graph Processing]], //Proceedings of the 42nd International Symposium on | Parallel Graph Processing]], //Proceedings of the 42nd International Symposium on | ||
| Computer Architecture (ISCA), Portland, OR, June 2015.// | Computer Architecture (ISCA), Portland, OR, June 2015.// | ||
| + | - Vivek Seshadri et al., [[http://users.ece.cmu.edu/~omutlu/pub/in-DRAM-bulk-AND-OR-ieee_cal15.pdf | Fast Bulk Bitwise AND and OR in DRAM]], //IEEE Computer Architecture Letters (CAL), April 2015.//** [Review Required]** | ||
| + | |||
| + | ==== Optional Readings Mentioned in Lecture ==== | ||
| + | - Smith, [[http://www.cs.utexas.edu/users/mckinley/notes/reviewing-smith.pdf | Task of the Referee]],// IEEE Computer 1990//. | ||
| + | - Hill and McKinley, [[http://www.cs.utexas.edu/users/mckinley/notes/reviewing.html|Notes on Constructive and Positive Reviewing]] | ||
| + | - Thomas Moscibroda and Onur Mutlu, [[http://users.ece.cmu.edu/~omutlu/pub/mph_usenix_security07.pdf | Memory Performance Attacks: Denial of Memory Service | ||
| + | in Multi-Core Systems]], //Proceedings of the 16th USENIX Security Symposium (USENIX SECURITY), | ||
| + | pages 257-274, Boston, MA, August 2007.// | ||