Reid: This week I worked on putting together the design proposal and setting up this fancy website. I also spent some time looking into new DRAM interfacing techniques including pivot options which will allow us to potentially switch to a new board if we are unable to make DRAM interface correctly on the ZedBoard. I also met with the Stay Square team from last semester to learn about their experiences interfacing with DRAM and other challenges in Vivado.
Teguh: This week I continued working on figuring out how to interface with DRAM on the ZedBoard from the PL. So far we've tried a large variety of approaches that are varying degrees of broken. The most promising approach was to instantiate a Xilinx AXI4 wrapper and expand from the sample code, but this resulted in the system failing to return any read requests. I also had grad school visit days which has limited how much I've been able to do this week.
Reid: This week I was able to integrate the FPGA fabric with the DRAM on the ZedBoard. We now have a DRAM controller which is working quite well to read and write 16 word blocks. I also was able to setup a fake boot loader to preload the DRAM with a pattern of integers. We have made a lot of progress over the past two weeks and feel much more confident about the trajectory of the project; however, we still are fairly far behind compared to where we would like to be and also need to balance workload in other courses. The next challenge I will likely tackle is finishing integrating the memory subsystem with the rest of the board and preparing for the project midpoint demos.
Teguh: After Reid was able to integrate the DRAM with the PL side of the ZedBoard, I began working on the various parts that are needed to get VGA output working and interfaced with memory, such as character bitmaps and other functionality so we can use our VGA driver as VGA Text Mode in our programs.
Reid: This week I spent the majority of my time writing tests for the memory subsystem. It seems like we are just about ready to connect it to the core. Overall our schedule is looking pretty dire as there is a lot more work to do and not much time left.
Teguh: While we have more functionality available to us with interfacing to the DRAM, we still needed to test and debug various parts of the system. Our implementation of VGA text mode is just about working, so most of the work I've been doing has been integrating it and testing it with the memory subsystem.
Reid: This week I finished validating the memory controller and started integrating it with the core. For the demo we weren't able to show everything integrated yet, but we were able to demonstrate the individual parts of the system (VGA display, memory controller, core simulation)
Teguh: Got VGA working in Text Mode with VRAM and DRAM successfully communicating with eachother. Working next on integrating the RISC-V core with the now complete memory subsystem so we can run more interesting things on it.
Reid: This week I finished integrating the core with the rest of the system. We now can run all 447 tests. Our next step is to begin working on synthesizing the full chip on the board.
Teguh: Working on getting the now integrated core to synthesize to the FPGA, as well as looking into what will be needed for PS/2 and timer interrupts in the near future.
Reid: This week we worked on getting the processor to meet timing. Some of the key microarchitectural changes that have been implemented include switching to a two stage instruction fetch, a two stage execute (branch resolution in EX2), a two memory stages, and introducing a pre-register in front of the branch prediction table write operations. We are also slowing down the frequency to 80MHz and tweaking the Vivado synthesis strategies to hopefully allow the design to meet timing and begin working on the board. In addition, I worked on integrating the synthesis process with the make file. There is a python script that will setup the directory structure and then generate a Vivado TCL script which will load the project, hook up all of the IP cores, and then run synthesis. This has turned out to be much more reliable than the GUI.
Teguh: We are working on getting the CPU to meet timing constraints in Vivado.
Reid: This week I worked on getting the infrastructure set up to begin running kernels and booting the processor. This was the most successful week so far in the project. We are able to boot arbitrary programs and run them on the processor on the Zedboard. I also started working on cleaning up the atomic instruction implementation and began investigating interrupt delivery.
Teguh: Working on adding support for the PS/2 keyboards. Have the keyboard producing valid set 1 scancodes that need to be added to the processor. Working on mimicking the VRAM to allow polling on the keyboard scan codes, and ultimately provide interrupts to the CPU.
Reid: I worked on improving hardware counter support and adding additional system instructions. In addition I worked on the final presentation.
Teguh: Keyboard is now integrated with the core. Few minor bugs with the implementation of the scan code buffer that need to be resolved so we get accurate and responsive input. VGA colors look fine, started porting Tetris.