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This week I focused on fixing some small bugs with the peripherals, mostly spending time pipelining the graphics to avoid spurious patches of color in both TEXT and LOWRES graphics modes. In addition to this, I spent time working on the CAD file for the computer case which will be 3D printed for our final demo on Friday, May 1st.
Will’s Status Report 04/18
This week I completed and tested the read sequence with the floppy disk emulator and worked on debugging the write sequence. The read sequence works well, but there are still some issues with writing. Particularly, it seems that the write timing is slightly out of synch between the FPGA and the floppy disk, resulting in corrupted tracks. To resolve this issue, I am using a disk image editor and a FDD-to-hex translator to identify where errors happen.
Will’s Status Report 4/4
This week I worked with Rudy and Aaron for early integration steps. After demo, I also made some changes to the keyboard module to make it capable of sending control characters (e.g. CTRL + C, CTRL + G, etc.). Additionally, I have begun testing the FDD control card in hardware and have formatted a handful of emulated disk images to assist in testing. Should this go smoothly, I hope to start running the DOS3.2 RWTS by the end of next weekend. More results will be available tomorrow (Sunday, 4/5).
Overall the major risk associated with testing disk is that debugging may be tremendously difficult (and will require using an oscilloscope over multiple test runs and stitching them together).
Will’s Status Report 03/28
This week I made a module to display the contents of video memory to a monitor in LOWRES and TEXT graphics graphics modes. This module was adapted from the vga module written earlier this semester by adding hardware to raster through video memory and adding translators from byte data to graphical data. I also updated the keyboard interface to work with the rest of our integrated design.
Will’s Status Report 03/21
This week I almost completely finished verifying the floppy disk control card in simulation ensuring that it is compatible with both the Disk ii FDD and our implementation of the 6502. During testing I found several issues with the FDD firmware that were re-written to align with the microinstructions of our implementation of the 6502. Further changes may need to be made for the read sequence to function properly, but testing so far indicates that the FDD is fully functional.
Moving into next week, I need to spend time starting to write device drivers for the peripheral modules. Aaron and I plan to meet and talk about the FDD drivers, as they are a critical and significant part of the DOS.
Will’s Status Report for 3/14
I spent this week testing the FDD control card in simulation. The testing process has come with some challenges, especially because the FDD control card is meant to be controlled by the 6502 (which is not included in the test structure). Instead of using the 6502, I am carefully toggling the signals on the control card to emulate RWTS sequences and making sure the output of the control card follows as expected. There are a handful of output waveforms available online that can be used to check if the emulator is working properly.
Overall, this portion of the project is on track for our “Testing and Verification” weeks.
For next week, I hope to have the FDD control card fully tested and have some testing done on the other peripherals. I also would like to start writing the peripheral drivers.
Will’s Weekly Status Report 02/28
This week the RTL for the floppy disk control card was completed and I began testing it in simulation. Alongside finishing the RTL, some testing was done with the FDD emulator in preparation for integration testing coming in a few weeks. There were some challenges associated with the timing requirements of the FDD, but many of these were resolved after some coordination with Rudy on the 6502 microinstructions associated with disk reads and writes.
On the project management side, the FDD is on track to be completed on time for the upcoming testing and verification weeks.
Will’s Weekly Status Report 02/21
This week I began implementing the floppy disk controller in RTL as well as submitted order forms (or will be submitting order forms) for most parts related to the Apple // peripherals. After spending last week primarily on documentation for the FDD control hardware and software, I am feeling confident that the floppy disk interface will be functional in synthesis (on the Altera DE2-115) by the time we have access to a real disk drive to test with.
Alongside the FDD RTL I wrote this week, I have also been documenting some of the software quirks associated with the RWTS (Read or Write, Track and Sector) protocol of the DOS. Because the floppy disk is not clocked (and is technically largely controlled by internal analog signals) there are some unique timing constraints associated with syncing the 6502 to a floppy disk during writes. These are mostly handled by a timer on the FDD control card, but the clock period connected to this tuner may need to be ‘tuned’ so that the data reading/writing rate is correct.
Beyond the above notes, the completion of the peripherals is on schedule and should be ready to be integrated on schedule.
Will’s Status Report for 02/14
This week I continued to work on documenting and implementing peripheral modules for our Apple //. My time was especially spent researching the different pieces of software and hardware used to control the floppy disk drive (FDD). One of the quirks of the Apple // was that the FDD is primarily controlled by software and the DOS – a control scheme that was not conventionally used in other floppy disk based systems. The Apple // was implemented in this way to minimize hardware costs, meaning the Disk // control card should be relatively simple to implement. Our main concern with implementing the Disk // control card is that because the FDD is primarily software defined, our hardware must perfectly match the original Disk // control card.
In addition to working on the FDD controller, I implemented some useful modules for interfacing the 6502 with a keyboard and monitor.
Currently, we are on schedule to finish the peripheral modules and drivers as planned.