Team Status Report for 2/7

Writing the 6502 provided us a bit more complications than initially expected, which are described in Rudy’s status report for this week. However, since writing the 6502 was scheduled to take 3 weeks, we are still on time for this goal. These complications resulted in a discussion between Rudy and Aaron to create a plan for the redesign of the 6502, making it compatible with the requirements of a FPGA. Below are the steps we’ve decided are necessary for the redesign:

1. Determining microinstructions for each addressing mode, this will translate into control signals
2. Deciding necessary hardware for the functionality for each instruction, such as addition and register transfers
3. Listing out all possible inputs into each register
4. Translate these hardware requirements into a block diagram
5. Translate block diagram into Verilog

For the 6502 testbench, we have set up a very basic testbench to run simulations when we start writing the Verilog. However, the only test programs we can currently run are pre-existing ones. Thus, we are also currently setting up a way to compile C code, so that we can run other benchmarks.

Currently, we appear to be on track and no significant risks pose themselves. However, if things go on a downturn with the 6502 redesign, there is a mitigation plan of using an open-source 6502 core.

Beyond the 6502, researching and implementing the FDD module may prove to be challenging. The original motherboard of the Apple ii needed an additional control card to interface with the Disk-ii floppy disk drive. Most of the functionality of the control card can be implemented on FPGA, but some additional hardware (breadboard, MOSFET, power supply, etc.) will be needed to drive the stepper motors. If it is not possible to recreate the control card using our FPGA, there is an FDD control card emulator that we can buy and use instead.

No schedule update has occurred.