This week, the focus was on packaging and clearing our user interface system in order to start getting feedback form people that can trial our system.
This week I managed to get the power and timing parameters achieved to be printed on the side of the screen in a location that I thought was unobtrusive. It’s one of the details that I would like to verify in our user feedback form.
Additionally, given that we are moving from an Ultra96v2 FPGA to a Kria based FPGA, we would need to learn how to use a different set of EDA tools. So I spent the past week mainly focussing on how to operate and use Vitis to synthesize our softcores and language models.
Over the next week my goals are:
- I want to work out how the full synthesis flow to load our models onto the Kria works.
- I want to see how to move data onto the FPGA and pull the results out of the FPGA works, this way I can extend our previous python script to use the FPGA for inference.
After this, I would plan to go for the more advanced power and performance data that we want to monitor on the FPGA.
We’re currently well ahead of schedule and on track to reach the iteration and architecture phase within another 2 weeks.