This past week, I contributed to the design slides. I focused on the design requirements and the implementation details, specifically the hardware optimizations that we can implement on the FPGA for motion planning. The creating of these slides also led me to think about the format we’ll put our collision data in for transfer to the FPGA.
This week I also worked on getting the Vitis HLS environment set up by running an example project on the Ultra96 FPGA. This example project was a kernel that summed up two vectors that were 1024 elements long each. I built the hardware target, and loaded the disk image onto the micro SD card. The FPGA did not boot up, and I am suspicious of the FPGA itself—I had set up the HLS environment for the Ultra96-v2, which we used in 18-643, but this FPGA model is the Ultra96-v1. Because of this, I’ll have to do some digging to figure out what needs to change about the development environment so that I can build for the Ultra96-v1.
This upcoming week, I will try to wrap up setting up the HLS environment. I will also try to finish the octree implementation, so that it has a complete interface that will be useful later when we are actually using the FPGA for acceleration. I will be working on the design report as well with the rest of the team.