Donovan’s Status Report 4/16

Earlier this week, I was working on producing a new division module that complied with the double precision format of the AGC architecture, as my previous design did not.  Unfortunately, a few implementation details prolonged that work, and as a team, we decided that DV and DDOUBLE instructions would move lower on our list of priorities.  Putting that aside, we shifted focus to our CPU’s UART interface, by which the I/O registers communicate with the outside world.  I implemented and tested a module that receives an update stream for the CPU’s input registers, byte-by-byte, from a unit (courtesy of Ben Marshall on GitHub) that already handles receiving the data bit-by-bit.  My unit then updates the CPU’s input registers as the data is received.  We have begun the first leg of high-level integration and validation.  Next week, I plan to assist in this process as well as prepare for the final presentation.