Our most significant risks as of now consist of the probability of dropping packets during our communication protocols. The packets that we send are carefully crafted to contain information that the hashing modules will need so we need to make sure that the packets won’t get dropped or corrupted. This might become more of a problem when we start to scale up our design to more FPGA boards because our current plan includes using a breadboard and the Pi Wedge to bridge the connections between the GPIO pins between the Raspberry Pi and the FPGAs. By including checksums or other types of CRCs, we can diminish the effects of dropped bits by detecting them before computation. However, the inclusion of CRCs will eat into our communication budget and is not a solution for the RPI to breadboard interconnect.Through further research, we are examining whether the plans we have in place are feasible. If communication bandwidth proves to be an issue, we have a contingency plan to increase the number of bits sent by our SPI protocol from one to eight. This should reduce any bottlenecks caused by communication.
We didn’t make any changes to the requirements this week. The specifications we laid out in the proposal are still the guiding principles of the project. This week, we as a team fleshed out more about the communication protocol and how we plan on performing the choosing algorithm. On the communication side of things, we fleshed out what our data packets would look like and what the different fields inside of the packets would contain. We also discussed the possibility of packets dropping and discussed sending ACK packets that would help network traffic confirmation. In regards to the choosing algorithm, we want to generate a bunch of hashing modules and have a select line input to decide what the hashing modules will compute.
The progress of the project is going well with a large portion of the research completed and some implementation occurring already. We still need further concrete details on how each hashing algorithm will be translated into SystemVerilog. With the delivery of the Raspberry Pi and Pi Wedge next week and the inventory of FPGAs already in hand, we anticipate being able to perform testing in the weeks to come. Because of this setback, we also have to push back our planned parallel testing of our modules. The expected completion dates for that will be pushed back accordingly with the arrival of our Pi components.
