For this week, I met up with a TA to discuss our issues in the communication modules between the Pi and the FPGA. The reasons we are dropping bits are mostly likely due to the fact that the clock is shorted and the FPGA is not sending on a frequency that the Pi can operates. Right now the pi is the host, but the FPGA is sending the clock signal instead of the Pi. When using the SPI library, the Pi also sends in a clock signal, so our clock signal is shorted which affected the results when we are receiving signal from the FPGA. The TA suggested a solution which involves changes on the SPI code on the FPGA side. I already informed my teammates about the TA’s suggestion and we will see if we can work something out. In the mean time, I’m working on the presentation slides that are due on Sunday. In terms of schedule, I think I’m behind since I need to wait for the FPGA side’s SPI code to change to test my SPI code on the Pi. I will continue to work with my teammates to resolve this issue.