Ben’s Status Report (10/3)

This week, I focused mainly on starting the RTL implementation of the memory subsystem and turning the architecture I had planned over the previous weeks into actual modules. I worked on defining the CPU-to-memory interface with Josh and started implementing the basic RAM, BIOS ROM, and address-decoding logic that will sit between the 8088 and the rest of the system. I also worked through how memory reads and writes should be handled and how the decoder will determine whether a CPU request should go to RAM, ROM, or eventually one of the peripheral interfaces.  I also started setting up simple directed tests for RAM read/write behavior, ROM reads, and address-boundary cases so that each piece can be verified before integrating it with the CPU. This helped clarify some of the timing and interface details that still need to be agreed on between the CPU and memory sides. My progress is currently on schedule, and next week I plan to finish the initial memory modules and tests, connect them more closely to Josh’s CPU interface, and begin working on the next layer of the peripheral system, starting with the I/O decode and storage interface.