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lab5_faq [2014/03/30 20:09]
varun
lab5_faq [2014/12/11 00:09] (current)
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 ===== Lab 5 FAQs ===== ===== Lab 5 FAQs =====
 +
 +  * (Q) Do we need to update the BTB for conditional branches that have been predicated out by having the target set as PC+4 in the BTB during the execute stage as well? Or should the target be the target of the branch if it were taken? Anyone who has finished the branch predictor know this? I am failing random tests and I think its because I am updating the BTB with pc+4 for a predicated out instruction.
 +    * (A) You should be storing the target of the branch, as PC+4 will always be assumed should the branch not be taken.
 +
 +  * (Q) Is there any way to see the debug statements that are printed when we #define DEBUG, or any printf statement? The only output I can ever get is the refsim comparison.
 +    * (A) You can run the simulator by itself w/o make verify
 +
 +  * (Q) BTB Unconditional Bit?  Do we still need to have an unconditional bit per entry in the BTB?
 +    * (A) Yes
  
   * (Q) Are we allowed to modify the existing Pipe_Op struct provided to us?   * (Q) Are we allowed to modify the existing Pipe_Op struct provided to us?
lab5_faq.1396210170.txt.gz ยท Last modified: 2014/12/11 00:09 (external edit)