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===== Processor Manuals ===== | ===== Processor Manuals ===== | ||
+ | |||
+ | ==== ARM ==== | ||
+ | Throughout this course, we will use the ARM Architecture Reference Manual as the definitive specification for the ARM ISA. All other ARM-related material provided below are only for your benefit. | ||
+ | * ARM Architecture Reference Manual | ||
+ | * [[https://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf|Manual (5MB)]] | ||
+ | * ARM Architecture Instruction Quick Reference | ||
+ | * {{arm-instructionset.pdf|Quick Ref (.5MB)}} | ||
==== MIPS ==== | ==== MIPS ==== | ||
- | Throughout this course, we will use the MIPS R4000 User's Manual (1994) as the definitive specification for the MIPS ISA. All other MIPS-related material provided below are only for your benefit. | + | All MIPS-related material provided below are only for your benefit. These manuals are used in older version of this class. |
* {{mips_r4000_users_manual.pdf| (1.5MB) MIPS R4000 Microprocessor User’s Manual (1994)}} | * {{mips_r4000_users_manual.pdf| (1.5MB) MIPS R4000 Microprocessor User’s Manual (1994)}} | ||
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* (Note: IA-64 is different from Intel 64 and is **not** an x86 ISA.) | * (Note: IA-64 is different from Intel 64 and is **not** an x86 ISA.) | ||
- | ==== ARM ==== | ||
- | * ARM Architecture Reference Manual | ||
- | * [[https://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf|Manual (5MB)]] | ||
- | * ARM Architecture Instruction Quick Reference | ||
- | * {{arm-instructionset.pdf|Quick Ref (.5MB)}} | ||
==== Alpha ==== | ==== Alpha ==== | ||
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* ''xst.pdf'': [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst.pdf|XST User Guide for Virtex-4, | * ''xst.pdf'': [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst.pdf|XST User Guide for Virtex-4, | ||
Virtex-5, Spartan-3, and Newer CPLD Devices 14.2 (2010)]] | Virtex-5, Spartan-3, and Newer CPLD Devices 14.2 (2010)]] | ||
+ | |||
+ | ==== Verilog Tutorials ==== | ||
+ | While this class will focus on System Verilog, these Verilog manuals are useful for additional studies: | ||
+ | * {{synth-verilog-cummins.pdf|Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}} | ||
+ | * {{goodrtl-parkin.pdf|Parkin, Writing Successful RTL Descriptions in Verilog}} | ||
+ | * {{18447-sv-to-verilog.pdf|18-447 Handout: Moving from System Verilog to Verilog}} | ||
+ | * [[http://users.ece.utexas.edu/~patt/12s.382N/tools/verilog_manual.html|Online Verilog Manual (UT-Austin EE 382N)]] |