techdocs
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
|
techdocs [2014/01/11 15:23] rachata |
techdocs [2014/01/12 22:48] varun |
||
|---|---|---|---|
| Line 16: | Line 16: | ||
| * (Note: IA-64 is different from Intel 64 and is **not** an x86 ISA.) | * (Note: IA-64 is different from Intel 64 and is **not** an x86 ISA.) | ||
| + | ==== ARM ==== | ||
| + | * ARM Architecture Reference Manual | ||
| + | * [[https://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf|Manual (5MB)]] | ||
| + | * ARM Architecture Instruction Quick Reference | ||
| + | * {{arm-instructionset.pdf|Quick Ref (.5MB)}} | ||
| ==== Alpha ==== | ==== Alpha ==== | ||
| Line 37: | Line 42: | ||
| * ''xst.pdf'': [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst.pdf|XST User Guide for Virtex-4, | * ''xst.pdf'': [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/xst.pdf|XST User Guide for Virtex-4, | ||
| Virtex-5, Spartan-3, and Newer CPLD Devices 14.2 (2010)]] | Virtex-5, Spartan-3, and Newer CPLD Devices 14.2 (2010)]] | ||
| - | |||
| - | ===== Verilog Tutorials ===== | ||
| - | * {{synth-verilog-cummins.pdf|Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}} | ||
| - | * {{goodrtl-parkin.pdf|Parkin, Writing Successful RTL Descriptions in Verilog}} | ||
| - | * {{18447-sv-to-verilog.pdf|18-447 Handout: Moving from System Verilog to Verilog}} | ||
| - | * [[http://users.ece.utexas.edu/~patt/12s.382N/tools/verilog_manual.html|Online Verilog Manual (UT-Austin EE 382N)]] | ||
techdocs.txt · Last modified: 2015/04/20 22:40 by rachata
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
