This shows you the differences between two versions of the page.
Next revision | Previous revision Next revision Both sides next revision | ||
techdocs [2014/01/11 15:22] rachata created |
techdocs [2014/01/13 00:02] rachata |
||
---|---|---|---|
Line 4: | Line 4: | ||
===== Processor Manuals ===== | ===== Processor Manuals ===== | ||
+ | |||
+ | ==== ARM ==== | ||
+ | Throughout this course, we will use the ARM Architecture Reference Manual as the definitive specification for the ARM ISA. All other ARM-related material provided below are only for your benefit. | ||
+ | * {{arm_full_reference.pdf|ARM Architecture Reference Manual}} | ||
+ | * {{arm-instructionset.pdf|ARM Instruction Set (pdf)}} | ||
==== MIPS ==== | ==== MIPS ==== | ||
- | Throughout this course, we will use the MIPS R4000 User's Manual (1994) as the definitive specification for the MIPS ISA. All other MIPS-related material provided below are only for your benefit. | + | All MIPS-related material provided below are only for your benefit. These manuals are used in older version of this class. |
* {{mips_r4000_users_manual.pdf| (1.5MB) MIPS R4000 Microprocessor User’s Manual (1994)}} | * {{mips_r4000_users_manual.pdf| (1.5MB) MIPS R4000 Microprocessor User’s Manual (1994)}} | ||
Line 12: | Line 17: | ||
* {{mips_tutorial.pdf|MIPS Tutorial (pdf)}} | * {{mips_tutorial.pdf|MIPS Tutorial (pdf)}} | ||
* {{mips_tutorial.ppt|MIPS Tutorial (ppt)}} | * {{mips_tutorial.ppt|MIPS Tutorial (ppt)}} | ||
- | |||
==== x86 ==== | ==== x86 ==== | ||
Line 25: | Line 29: | ||
* (Note: IA-64 is different from Intel 64 and is **not** an x86 ISA.) | * (Note: IA-64 is different from Intel 64 and is **not** an x86 ISA.) | ||
+ | ==== ARM ==== | ||
+ | * ARM Architecture Reference Manual | ||
+ | * [[https://www.scss.tcd.ie/~waldroj/3d1/arm_arm.pdf|Manual (5MB)]] | ||
+ | * ARM Architecture Instruction Quick Reference | ||
+ | * {{arm-instructionset.pdf|Quick Ref (.5MB)}} | ||
==== Alpha ==== | ==== Alpha ==== | ||
Line 42: | Line 51: | ||
* {{lc3b-figures.pdf|LC-3b Figures from Appendix C}} | * {{lc3b-figures.pdf|LC-3b Figures from Appendix C}} | ||
* {{18447-lc3b-pipelining.pdf|Pipelined LC-3b Microarchitecture}} | * {{18447-lc3b-pipelining.pdf|Pipelined LC-3b Microarchitecture}} | ||
- | |||
===== Software Tools ===== | ===== Software Tools ===== | ||
- | |||
- | ==== SPIM Simulator ==== | ||
- | * [[http://pages.cs.wisc.edu/~larus/xspim.pdf|Getting Started with xspim]] | ||
==== Cadence ==== | ==== Cadence ==== | ||
Line 58: | Line 63: | ||
Virtex-5, Spartan-3, and Newer CPLD Devices 14.2 (2010)]] | Virtex-5, Spartan-3, and Newer CPLD Devices 14.2 (2010)]] | ||
- | ===== Verilog Tutorials ===== | + | ==== Verilog Tutorials ==== |
+ | While this class will focus on System Verilog, these manuals are useful for additional studies: | ||
* {{synth-verilog-cummins.pdf|Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}} | * {{synth-verilog-cummins.pdf|Cummings, Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill}} | ||
* {{goodrtl-parkin.pdf|Parkin, Writing Successful RTL Descriptions in Verilog}} | * {{goodrtl-parkin.pdf|Parkin, Writing Successful RTL Descriptions in Verilog}} | ||
* {{18447-sv-to-verilog.pdf|18-447 Handout: Moving from System Verilog to Verilog}} | * {{18447-sv-to-verilog.pdf|18-447 Handout: Moving from System Verilog to Verilog}} | ||
* [[http://users.ece.utexas.edu/~patt/12s.382N/tools/verilog_manual.html|Online Verilog Manual (UT-Austin EE 382N)]] | * [[http://users.ece.utexas.edu/~patt/12s.382N/tools/verilog_manual.html|Online Verilog Manual (UT-Austin EE 382N)]] |