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readings [2015/03/31 17:09] kevincha |
readings [2015/04/01 18:51] albert |
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===== Lecture 24 (3/30 Mon.) ===== | ===== Lecture 24 (3/30 Mon.) ===== | ||
**Required:** | **Required:** | ||
+ | * {{http://users.ece.cmu.edu/~omutlu/pub/mutlu_hpca03.pdf | Mutlu et al., “Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-order Processors,” HPCA 2003.}} | ||
+ | * {{http://users.ece.cmu.edu/~omutlu/pub/TR-HPS-2006-006.pdf|Srinathet al., “Feedback directed prefetching”, HPCA 2007.}} | ||
**Mentioned During Lecture:** | **Mentioned During Lecture:** | ||
* {{ramulator.pdf|Kim et al., “Ramulator: A Fast and Extensible DRAM Simulator,” IEEE Computer Architecture Letters 2015.}} | * {{ramulator.pdf|Kim et al., “Ramulator: A Fast and Extensible DRAM Simulator,” IEEE Computer Architecture Letters 2015.}} | ||
+ | * {{http://users.ece.cmu.edu/~omutlu/pub/eaf-cache_pact12.pdf|Seshadri et al., “The Evicted-Address Filter: A Unified Mechanism to Address Both Cache Pollution and Thrashing,”PACT 2012.}} | ||
+ | * {{http://hps.ece.utexas.edu/pub/TR-HPS-2010-002.pdf|Lee et al., “DRAM-Aware Last-Level Cache Writeback: Reducing Write-Caused Interference in Memory Systems,”HPS Technical Report, April 2010.}} | ||
+ | * {{tldram-lee.pdf| Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,” HPCA 2013. (Sections 1 and 2)}} | ||
+ | * {{2012_isca_salp.pdf| Kim et al., “A Case for Subarray-Level Parallelism (SALP) in DRAM,” ISCA 2012. (Sections 1 and 2)}} | ||
+ | * {{http://users.ece.cmu.edu/~omutlu/pub/rlmc_isca08.pdf|Ipek et al., “Self Optimizing Memory Controllers: A Reinforcement Learning Approach,”ISCA 2008}} | ||
+ | * {{http://users.ece.cmu.edu/~omutlu/pub/mutlu_ieee_micro06.pdf|Mutlu et al., "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance," ISCA 2005, IEEE Micro Top Picks 2006.}} | ||
+ | * {{http://users.ece.cmu.edu/~omutlu/pub/mutlu_micro05.pdf|Mutlu et al., "Address-Value Delta (AVD) Prediction," MICRO 2005.}} | ||
+ | * {{http://users.ece.cmu.edu/~omutlu/pub/armstrong_micro04.pdf|Armstrong et al., "Wrong Path Events," MICRO 2004.}} | ||
+ | |||
+ | ===== Lecture 25 (4/1 Wed.) ===== | ||
+ | **Required:** | ||
+ | * {{main-memory-system_kiise15.pdf| Onur Mutlu, Justin Meza, and Lavanya Subramanian, "The Main Memory System: Challenges and Opportunities," Invited Article in Communications of the Korean Institute of Information Scientists and Engineers (KIISE), 2015.}} | ||
+ | |||
+ | **Mentioned During Lecture:** | ||
+ | * {{jouppi1990.pdf|Jouppi, “Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers,” ISCA 1990.}} | ||
+ | * {{http://users.ece.cmu.edu/~omutlu/pub/TR-HPS-2006-006.pdf|Srinathet al., “Feedback directed prefetching”, HPCA 2007.}} |