User Tools

Site Tools


readings

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision Both sides next revision
readings [2015/02/28 07:15]
jeremie
readings [2015/03/02 22:10]
jeremie
Line 218: Line 218:
   * P&H Chapters 5.1-5.3 (cache chapters)   * P&H Chapters 5.1-5.3 (cache chapters)
   * Hamacher et al. Chapters 8.1-8.7 (cache/​memory chapters)   * Hamacher et al. Chapters 8.1-8.7 (cache/​memory chapters)
 +
 +**Mentioned During Lecture:**
   * {{A_Study_of_replacement_algorithms_for_a_virtual-storage_computer.pdf|qBelady,​ “A study of replacement algorithms for a virtual-storage computer,​” IBM Systems Journal, 1966.}}   * {{A_Study_of_replacement_algorithms_for_a_virtual-storage_computer.pdf|qBelady,​ “A study of replacement algorithms for a virtual-storage computer,​” IBM Systems Journal, 1966.}}
 +
 +===== Lecture 19 (3/2 Mon.) =====
 +**Required:​**
 +  * {{wilkes_-_1965_-_slave_memories_and_dynamic_storage_allocation.pdf|Wilkes,​ M. V. (1964). Slave Memories and Dynamic Storage Allocation. IEEE Transactions on Electronic Computers.}}
 +  * {{A_Case_For_MLP_Aware_Cache_Replacement.pdf|Qureshi et al., “A Case for MLP-Aware Cache Replacement,​“ ISCA 2006.}}
 +  * P&H Chapters 5.1-5.3 (cache chapters)
 +  * Hamacher et al. Chapters 8.1-8.7 (cache/​memory chapters)
 +
 +**Mentioned During Lecture:**
 +  * {{jouppi_-_1990_-_improving_direct-mapped_cache_performance_by_the_addition_of_a_small_fully-associative_cache_and_prefetch_buffers.pdf|Jouppi,​ N. P. (1990). Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers. Proceedings of the 17th annual international symposium on Computer Architecture.}}
 +  * {{mutlu_et_al._-_2003_-_runahead_execution_an_alternative_to_very_large_instruction_windows_for_out-of-order_processors.pdf|Mutlu,​ O., Stark, J., Wilkerson, C., & Patt, Y. N. (2003). Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. Proceedings of the 9th International Symposium on High-Performance Computer Architecture.}}
 +  * {{seznec_a_case_for_two_way_skewed_associative_caches.pdf|Seznec. A Case for Two-Way Skewed-Associative Caches. ISCA 1993.}}
 +  * {{seznec_a_case_for_two_way_skewed_associative_caches.pdf|Kroft. Lockup-Free Instruction Fetch/​Prefetch Cache Organization. ISCA 1981.}}
 +  * {{qureshi_utility_based_cache_partitioning.pdf|Qureshi and Patt. Utility-Based Cache Partitioning:​ A Low-Overhead,​ High-Performance,​ Runtime Mechanism to Partition Shared Caches. MICRO 2006.}}
 +  * {{suh_new_memory_monitoring_scheme_for_memory_aware_scheduling_and_partitioning.pdf|Suh et al. A New Memory Monitoring Scheme for Memory-Aware Scheduling and Partitioning. HPCA 2002.}}
readings.txt · Last modified: 2015/04/13 19:31 by kevincha