readings
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readings [2015/01/12 19:14] kevincha |
readings [2015/02/05 17:09] rachata |
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| * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/pp-appendixc.pdf|P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)]] | * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/pp-appendixc.pdf|P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)]] | ||
| * **P&H** stands for Patterson & Hennessy's //Computer Organization and Design: The Hardware/Software Interface// | * **P&H** stands for Patterson & Hennessy's //Computer Organization and Design: The Hardware/Software Interface// | ||
| + | |||
| + | ====== Guides on how to review papers critically ====== | ||
| + | * Lecture slides: {{onur-447-s15-how-to-do-the-paper-reviews.pdf | pdf}} {{onur-447-s15-how-to-do-the-paper-reviews.ppt | Slides ppt}} | ||
| + | * Example reviews on "Main Memory Scaling: Challenges and Solution Directions" (link to the paper) | ||
| + | * {{review-chapter.pdf | Review 1}} | ||
| + | * {{review-chapter-2.pdf | Review 2}} | ||
| + | * Example review on "Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems" (link to the paper) | ||
| + | * {{review-sms.pdf | Review 1}} | ||
| + | |||
| ===== Lecture 1 (1/12 Mon.) ===== | ===== Lecture 1 (1/12 Mon.) ===== | ||
| Line 45: | Line 54: | ||
| **Mentioned during lecture:** | **Mentioned during lecture:** | ||
| + | * {{paper_aklaiber_19jan00.pdf | Klaiber, "The Technology Behind CrusoeTM Processors", Transmeta White Paper, 2000}} | ||
| ===== Lecture 4 (1/21 Wed.) ===== | ===== Lecture 4 (1/21 Wed.) ===== | ||
| Line 71: | Line 81: | ||
| **Mentioned during lecture:** | **Mentioned during lecture:** | ||
| + | * {{bestway.pdf|Wilkes, M. V. (1951). The best way to design an automatic calculating machine. Manchester University Computer Inaugural Conference.}} | ||
| + | * [[http://research.microsoft.com/pubs/68221/acrobat.pdf |Butler W. Lampson, “Hints for Computer System Design,” ACM Operating Systems Review, 1983.]] | ||
| + | |||
| + | ===== Lecture 8 (2/2 Mon.) ===== | ||
| + | **Required:** | ||
| + | * P&H Sections 4.9-4.11 | ||
| + | * {{00476078.pdf|Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.}} | ||
| + | * {{00004607.pdf|Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.}} | ||
| + | * {{mcfarling_-_1993_-_combining_branch_predictors.pdf|Mcfarling, S. (1993). Combining branch predictors. WRL Technical Note TN-36.}} | ||
| + | * {{kessler_-_1999_-_the_alpha_21264_microprocessor.pdf|Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.}} | ||
| + | |||
| + | **Mentioned during lecture:** | ||
| + | * {{p16-pettis.pdf|Pettis, K., & Hansen, R. C. (1990). Profile guided code positioning. Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation.}} | ||
| + | |||
| + | ===== Lecture 9 (2/4 Wed.) ===== | ||
| + | **Required:** | ||
| + | * P&H Sections 4.9-4.11 | ||
| + | * {{00476078.pdf|Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.}} | ||
| + | * {{00004607.pdf|Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.}} | ||
| + | * {{mcfarling_-_1993_-_combining_branch_predictors.pdf|Mcfarling, S. (1993). Combining branch predictors. WRL Technical Note TN-36.}} | ||
| + | * {{kessler_-_1999_-_the_alpha_21264_microprocessor.pdf|Kessler, R. E. (1999). The Alpha 21264 Microprocessor. IEEE Micro.}} | ||
| + | |||
| + | **Mentioned during lecture:** | ||
| + | * {{flash-memory-data-retention_hpca15.pdf|Yu Cai, Yixin Luo, Erich F. Haratsch, Ken Mai, and Onur Mutlu, Data Retention in MLC NAND Flash Memory: Characterization, Optimization and Recovery, HPCA 2015.}} | ||
| + | * {{adaptive-latency-dram_hpca15.pdf|Donghyuk Lee, Yoongu Kim, Gennady Pekhimenko, Samira Khan, Vivek Seshadri, Kevin Chang, and Onur Mutlu, Adaptive-Latency DRAM: Optimizing DRAM Timing for the Common-Case, HPCA 2015.}} | ||
| + | * {{compression-aware-cache-management_hpca15.pdf|Gennady Pekhimenko, Tyler Huberty, Rui Cai, Onur Mutlu, Phillip P. Gibbons, Michael A. Kozuch, and Todd C. Mowry, Exploiting Compressed Block Size as an Indicator of Future Reuse, HPCA 2015.}} | ||
readings.txt · Last modified: 2015/04/13 19:31 by kevincha
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