readings
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readings [2015/01/12 18:48] kevincha |
readings [2015/01/16 19:29] kevincha [Lecture 3 (1/16 Fri.)] |
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| * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/pp-appendixc.pdf|P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)]] | * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/pp-appendixc.pdf|P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)]] | ||
| * **P&H** stands for Patterson & Hennessy's //Computer Organization and Design: The Hardware/Software Interface// | * **P&H** stands for Patterson & Hennessy's //Computer Organization and Design: The Hardware/Software Interface// | ||
| + | |||
| + | ====== Guides on how to review papers critically ====== | ||
| + | * Lecture slides: {{onur-447-s15-how-to-do-the-paper-reviews.pdf | pdf}} {{onur-447-s15-how-to-do-the-paper-reviews.ppt | Slides ppt}} | ||
| + | * Example reviews on "Main Memory Scaling: Challenges and Solution Directions" (link to the paper) | ||
| + | * {{review-chapter.pdf | Review 1}} | ||
| + | * {{review-chapter-2.pdf | Review 2}} | ||
| + | * Example review on "Staged memory scheduling: Achieving high performance and scalability in heterogeneous systems" (link to the paper) | ||
| + | * {{review-sms.pdf | Review 1}} | ||
| + | |||
| ===== Lecture 1 (1/12 Mon.) ===== | ===== Lecture 1 (1/12 Mon.) ===== | ||
| **Required:** | **Required:** | ||
| - | * None | + | * For HW1: {{00964437.pdf|Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.}} |
| **Mentioned during lecture:** | **Mentioned during lecture:** | ||
| Line 22: | Line 31: | ||
| * Memory Channel Partitioning", MICRO 2011.}} | * Memory Channel Partitioning", MICRO 2011.}} | ||
| * {{http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf|Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.}} | * {{http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf|Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.}} | ||
| + | * {{http://users.ece.cmu.edu/~omutlu/pub/memory-scaling_memcon13.pdf|Onur Mutlu, "Memory Scaling: A Systems Architecture Perspective" Technical talk at MemCon 2013 (MEMCON), Santa Clara, CA, August 2013.}} | ||
| + | * {{http://users.ece.cmu.edu/~kevincha/papers/chang_hpca2014.pdf|Kevin Chang, Donghyuk Lee, Zeshan Chishti, Alaa Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu, "Improving DRAM Performance by Parallelizing Refreshes with Accesses", In HPCA 2014, Orlando, Feb. 2014.}} | ||
| + | * {{http://users.ece.cmu.edu/~yoonguk/papers/kim-isca14.pdf | Yoongu Kim, Ross Daly, Jeremie Kim, Chris Fallin, Ji Hye Lee, Donghyuk Lee, Chris Wilkerson, Konrad Lai, Onur Mutlu, "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors", In ISCA-41, 2014.}} | ||
| ===== Lecture 2 (1/14 Wed.) ===== | ===== Lecture 2 (1/14 Wed.) ===== | ||
| Line 42: | Line 54: | ||
| **Mentioned during lecture:** | **Mentioned during lecture:** | ||
| + | * {{paper_aklaiber_19jan00.pdf | Klaiber, "The Technology Behind CrusoeTM Processors", Transmeta White Paper, 2000}} | ||
| ===== Lecture 4 (1/21 Wed.) ===== | ===== Lecture 4 (1/21 Wed.) ===== | ||
| Line 68: | Line 81: | ||
| **Mentioned during lecture:** | **Mentioned during lecture:** | ||
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readings.txt · Last modified: 2015/04/13 19:31 by kevincha
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