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--- readings [2015/01/10 21:02]
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+++ readings [2015/01/12 18:48]
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@@ Line 13: / Line 13: @@
 **Mentioned during lecture:**
+  * {{bstj29-2-147.pdf|Hamming, R. W. (1950). Error Detecting and Error Correcting Codes. Bell System Technical Journal, 29(2).}}
+  * {{youandyourresearch.pdf|Hamming, R. W. (1986). You and Your Research. Transcription of the Bell Communications Research Colloquium Seminar.}}
+    * [[http://www.youtube.com/watch?v=a1zDuOPkMSw|youtube]]
+  * {{p128-rixner.pdf|Rixner, S., Dally, W. J., Kapasi, U. J., Mattson, P., & Owens, J. D. (2000). Memory access scheduling. Proceedings of the 27th annual international symposium on Computer architecture.}}
+  * {{http://users.ece.cmu.edu/~omutlu/pub/mph_usenix_security07.pdf|Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.}}
+   * {{http://research.microsoft.com/pubs/79625/MICRO2007.pdf|Onur Mutlu and Thomas Moscibroda, "Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors", MICRO 2007. }}
+   * {{http://users.ece.cmu.edu/~omutlu/pub/memory-channel-partitioning-micro11.pdf|Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut Kandemir, and Thomas Moscibroda, "Reducing Memory Interference in Multicore Systems via Application-Aware
+   * Memory Channel Partitioning", MICRO 2011.}}
+   * {{http://users.ece.cmu.edu/~omutlu/pub/raidr-dram-refresh_isca12.pdf|Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.}}
+===== Lecture 2 (1/14 Wed.) =====
+**Required:**
+  * {{00964437.pdf|Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.}}
+  * {{moscibroda.pdf|Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.}}
+  * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/PP_Chap1.pdf|P&P Chapter 1 (Fundamentals)]]
+  * P&H Chapters 1 and 2 (Intro, Abstractions, ISA, MIPS)
+**Mentioned during lecture:**
+===== Lecture 3 (1/16 Fri.) =====
+**Required:**
+  * Note that you should familiarize yourself with these manuals. Please briefly skim through these manuals as you will probably need to refer to them while working on labs and homework
+  * MIPS Architecture Reference Manual
+    * {{mips_r4000_users_manual.pdf |Manual (the instruction set reference starts on pg.469)}}
+  * Intel® 64 and IA-32 Architectures Software Developer Manual (2013)
+    * [[http://download.intel.com/products/processor/manual/325462.pdf|(15MB) Combined Volumes 1-3]]3
+**Mentioned during lecture:**
+===== Lecture 4 (1/21 Wed.) =====
+**Required:**
+  * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/PP_Chap4.pdf|P&P Chapter 4 (The von Neumann Model)]]
+  * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/pp-appendixa.pdf|P&P Appendix A (The LC-3b ISA)]]
+  * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/pp-appendixc.pdf|P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)]]
+**Mentioned during lecture:**
+===== Lecture 5 (1/23 Fri.) =====
+**Required**
+  * None
+===== Lecture 6 (1/26 Mon.) =====
+**Required:**
+  * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/pp-appendixc.pdf|P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)]]
+  * P&H Appendix D (Mapping Control to Hardware)
+**Optional:**
+  * {{bestway.pdf|Wilkes, M. V. (1951). The best way to design an automatic calculating machine. Manchester University Computer Inaugural Conference.}}
+**Mentioned during lecture:**
+===== Lecture 7 (1/28 Wed.) =====
+**Required:**
+  * None
+**Mentioned during lecture:**

18-447 Introduction to Computer Architecture – Spring 2015

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