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readings [2014/05/20 01:46]
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readings [2014/05/20 04:22]
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 ** Mentioned during lecture: ** ** Mentioned during lecture: **
-  * Liu, Jaiyen, Veras, Mutlu, “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012. +  * {{raidr-isca12.pdf|Liu et al., “RAIDR: Retention-Aware Intelligent DRAM Refresh,” ISCA 2012.}} 
-  * Kim, Seshadri, Lee+, “A Case for Exploiting Subarray-Level Parallelism in DRAM,” ISCA 2012. +  * {{2012_isca_salp.pdf|Kim et al., “A Case for Exploiting Subarray-Level Parallelism in DRAM,” ISCA 2012.}} 
-  * Lee+, “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,​” HPCA 2013. +  * {{TLDRAM-Lee.pdf|Lee et al., “Tiered-Latency DRAM: A Low Latency and Low Cost DRAM Architecture,​” HPCA 2013.}} 
-  * Liu+, “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013. +  * {{p60-liu.pdf|Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013.}} 
-  * Seshadri+, “RowClone:​ Fast and Efficient In-DRAM Copy and Initialization of Bulk Data,” MICRO 2013. +  * {{rowclone_micro13.pdf|Seshadri ​et al., “RowClone:​ Fast and Efficient In-DRAM Copy and Initialization of Bulk Data,” MICRO 2013.}} 
-  * Pekhimenko+, “Linearly Compressed Pages: A Main Memory Compression Framework,​” MICRO 2013. +  * {{LCP.pdf|Pekhimenko ​et al., “Linearly Compressed Pages: A Main Memory Compression Framework,​” MICRO 2013.}} 
-  * Chang+, “Improving DRAM Performance by Parallelizing Refreshes with Accesses,​” HPCA 2014. +  * {{|Chang et al., “Improving DRAM Performance by Parallelizing Refreshes with Accesses,​” HPCA 2014.}} 
-  * Khan+, “The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study,” SIGMETRICS 2014. +  * {{error-mitigation-for-intermittent-dram-failures_sigmetrics14.pdf|Khan et al., “The Efficacy of Error Mitigation Techniques for DRAM Retention Failures: A Comparative Experimental Study,” SIGMETRICS 2014.}} 
-  * Luo+, “Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost,” DSN 2014. +  * {{luo_dsn14.pdf|Luo et al., “Characterizing Application Memory Error Vulnerability to Optimize Data Center Cost,” DSN 2014.}} 
-  * Kim+, “Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,” ISCA 2014. +  * Kim et al., “Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors,” ISCA 2014. 
-  * Lee, Ipek, Mutlu, Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,​” ISCA 2009, CACM 2010, Top Picks 2010. +  * {{meza_cal12.pdf|Meza et al., “Enabling Efficient and Scalable Hybrid Memories,​” IEEE Comp. Arch. Letters 2012.}} 
-  * Meza, Chang, Yoon, Mutlu, Ranganathan, “Enabling Efficient and Scalable Hybrid Memories,​” IEEE Comp. Arch. Letters 2012. +  * {{rowbuffer-aware-caching_iccd12.pdf|Yoon et al., “Row Buffer Locality Aware Caching Policies for Hybrid Memories,​” ICCD 2012.}} 
-  * Yoon, Meza et al., “Row Buffer Locality Aware Caching Policies for Hybrid Memories,​” ICCD 2012. +  * {{sttram_ispass13.pdf|Kultursay ​ et al., “Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative,​” ISPASS 2013. }} 
-  * Kultursay+, “Evaluating STT-RAM as an Energy-Efficient Main Memory Alternative,​” ISPASS 2013.  +  * {{meza_weed13.pdf|Meza  et al., “A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory,” WEED 2013.}} 
-  * Meza+, “A Case for Efficient Hardware-Software Cooperative Management of Storage and Memory,” WEED 2013. +  * {{ISCA09.pdf|Lee  et al. “Architecting Phase Change Memory as a Scalable DRAM Alternative,​” ISCA 2009.}}
-  * Lee, Ipek, Mutlu, Burger, ​“Architecting Phase Change Memory as a Scalable DRAM Alternative,​” ISCA 2009. +
-  * Meza+, “Enabling Efficient and Scalable Hybrid Memories,​” IEEE Comp. Arch. Letters, 2012. +
-  * Yoon, Meza et al., “Row Buffer Locality Aware Caching Policies for Hybrid Memories,​” ICCD 2012 Best Paper Award.+
readings.txt · Last modified: 2015/04/13 19:31 by kevincha