readings
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readings [2014/03/28 20:20] rachata |
readings [2014/04/02 20:25] rachata |
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| - | 1====== Readings ====== | + | ====== Readings ====== |
| * **P&P** stands for Patt & Patel's //Introduction to Computing Systems: From Bits and Gates to C and Beyond// | * **P&P** stands for Patt & Patel's //Introduction to Computing Systems: From Bits and Gates to C and Beyond// | ||
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| * {{raidr-isca12.pdf|Liu et al., RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012.}} | * {{raidr-isca12.pdf|Liu et al., RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012.}} | ||
| * {{2012_isca_salp.pdf|Kim et al., “A Case for Exploiting Subarray-Level Parallelism in DRAM, ISCA 2012.}} | * {{2012_isca_salp.pdf|Kim et al., “A Case for Exploiting Subarray-Level Parallelism in DRAM, ISCA 2012.}} | ||
| - | * {{:dram-retention-time-characterization_isca13.pdf|Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013.}} | + | * {{p60-liu.pdf|Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013.}} |
| * {{moscibroda.pdf|Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.}} | * {{moscibroda.pdf|Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.}} | ||
| * {{30470146.pdf|Mutlu, O., & Moscibroda, T. (2007). Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 146–160).}} | * {{30470146.pdf|Mutlu, O., & Moscibroda, T. (2007). Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 146–160).}} | ||
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| * {{raidr-isca12.pdf|Liu et al., RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012.}} | * {{raidr-isca12.pdf|Liu et al., RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012.}} | ||
| * {{2012_isca_salp.pdf|Kim et al., “A Case for Exploiting Subarray-Level Parallelism in DRAM, ISCA 2012.}} | * {{2012_isca_salp.pdf|Kim et al., “A Case for Exploiting Subarray-Level Parallelism in DRAM, ISCA 2012.}} | ||
| - | * {{:dram-retention-time-characterization_isca13.pdf|Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013.}} | + | * {{p60-liu.pdf|Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013.}} |
| * {{moscibroda.pdf|Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.}} | * {{moscibroda.pdf|Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.}} | ||
| * {{30470146.pdf|Mutlu, O., & Moscibroda, T. (2007). Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 146–160).}} | * {{30470146.pdf|Mutlu, O., & Moscibroda, T. (2007). Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (pp. 146–160).}} | ||
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| * {{p335-ebrahimi.pdf|Ebrahimi, E., Lee, C. J., Mutlu, O., & Patt, Y. N. (2010). Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems.}} | * {{p335-ebrahimi.pdf|Ebrahimi, E., Lee, C. J., Mutlu, O., & Patt, Y. N. (2010). Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems.}} | ||
| * {{p362-ebrahimi.pdf|Ebrahimi, E., Miftakhutdinov, R., Fallin, C., Lee, C. J., Joao, J. A., Mutlu, O., & Patt, Y. N. (2011). Parallel application memory scheduling. Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture.}} | * {{p362-ebrahimi.pdf|Ebrahimi, E., Miftakhutdinov, R., Fallin, C., Lee, C. J., Joao, J. A., Mutlu, O., & Patt, Y. N. (2011). Parallel application memory scheduling. Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture.}} | ||
| + | |||
| + | ===== Lecture 25 (4/2 Wed.) ===== | ||
| + | |||
| + | ** Mentioned during lecture: ** | ||
| + | * {{raidr-isca12.pdf|Liu et al., RAIDR: Retention-Aware Intelligent DRAM Refresh, ISCA 2012.}} | ||
| + | * {{p60-liu.pdf|Liu et al., “An Experimental Study of Data Retention Behavior in Modern DRAM Devices,” ISCA 2013.}} | ||
| + | * {{4299a065.pdf|Kim, Y., Papamichael, M., Mutlu, O., & Harchol-Balter, M. (2010). Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.}} | ||
| + | * {{muralidhara_et_al._-_2011_-_reducing_memory_interference_in_multicore_systems_via_application-aware_memory_channel_partitioning.pdf|Muralidhara, S. P., Subramanian, L., Mutlu, O., Kandemir, M., & Moscibroda, T. (2011). Reducing memory interference in multicore systems via application-aware memory channel partitioning. Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture.}} | ||
| + | * {{p335-ebrahimi.pdf|Ebrahimi, E., Lee, C. J., Mutlu, O., & Patt, Y. N. (2010). Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems.}} | ||
| + | * {{p362-ebrahimi.pdf|Ebrahimi, E., Miftakhutdinov, R., Fallin, C., Lee, C. J., Joao, J. A., Mutlu, O., & Patt, Y. N. (2011). Parallel application memory scheduling. Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture.}} | ||
| + | * {{isca08_ipek.pdf|Ipek, E., Mutlu, O., Martinez, J., Caruana, R. (2008). Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. Proceedings of the 42th Annual IEEE/ACM International Symposium on Microarchitecture.}} | ||
readings.txt · Last modified: 2015/04/13 19:31 by kevincha
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