readings
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
|
readings [2014/02/12 18:04] rachata |
readings [2014/03/19 03:15] rachata |
||
|---|---|---|---|
| Line 130: | Line 130: | ||
| * {{00476078.pdf|Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.}} | * {{00476078.pdf|Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.}} | ||
| * {{00004607.pdf|Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.}} | * {{00004607.pdf|Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.}} | ||
| + | |||
| + | ===== Lecture 13 (2/17 Mon.) ===== | ||
| + | ** Required ** | ||
| + | * none | ||
| + | |||
| + | ===== Lecture 14 (2/19 Wed.) ===== | ||
| + | ** Required ** | ||
| + | * {{p18-hwu.pdf|Hwu, W. W., & Patt, Y. N. (1987). Checkpoint repair for out-of-order execution machines. Proceedings of the 14th annual international symposium on Computer architecture.}} | ||
| + | * {{00476078.pdf|Smith, J. E., & Sohi, G. S. (1995). The microarchitecture of superscalar processors. Proceedings of the IEEE.}} | ||
| + | * {{00004607.pdf|Smith, J. E., & Pleszkun, A. R. (1988). Implementing precise interrupts in pipelined processors. Computers, IEEE Transactions on.}} | ||
| + | |||
| + | |||
| + | ===== Lecture 15 (2/21 Fri.) ===== | ||
| + | ** Required ** | ||
| + | * {{04523358.pdf|Lindholm, E., Nickolls, J., Oberman, S., & Montrym, J. (2008). NVIDIA Tesla: A Unified Graphics and Computing Architecture. Micro, IEEE.}} | ||
| + | * {{p50-fatahalian.pdf|Fatahalian, K., & Houston, M. (2008). A closer look at GPUs. Commun. ACM.}} | ||
| + | |||
| + | ===== Lecture 19 (3/19 Wed.) ===== | ||
| + | **Required:** | ||
| + | * P&H Chapters 5.1-5.3 (cache chapters) | ||
| + | * Hamacher et al. Chapters 8.1-8.7 (cache/memory chapters) | ||
| + | * {{wilkes_-_1965_-_slave_memories_and_dynamic_storage_allocation.pdf|Wilkes, M. V. (1965). Slave Memories and Dynamic Storage Allocation. IEEE Transactions on Electronic Computers.}} | ||
readings.txt · Last modified: 2015/04/13 19:31 by kevincha
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
