readings
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readings [2014/01/14 03:25] rachata |
readings [2015/01/11 16:16] kevincha |
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| * **P&P** stands for Patt & Patel's //Introduction to Computing Systems: From Bits and Gates to C and Beyond// | * **P&P** stands for Patt & Patel's //Introduction to Computing Systems: From Bits and Gates to C and Beyond// | ||
| + | * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/PP_Chap1.pdf|P&P Chapter 1 (Fundamentals)]] | ||
| + | * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/PP_Chap4.pdf|P&P Chapter 4 (The von Neumann Model)]] | ||
| + | * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/pp-appendixa.pdf|P&P Appendix A (The LC-3b ISA)]] | ||
| + | * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/pp-appendixc.pdf|P&P Appendix C (The Microarchitecture of the LC-3b, Basic Machine)]] | ||
| * **P&H** stands for Patterson & Hennessy's //Computer Organization and Design: The Hardware/Software Interface// | * **P&H** stands for Patterson & Hennessy's //Computer Organization and Design: The Hardware/Software Interface// | ||
| - | ===== Lecture 1 (1/13 Mon.) ===== | + | ===== Lecture 1 (1/12 Mon.) ===== |
| **Required:** | **Required:** | ||
| * None | * None | ||
| Line 10: | Line 14: | ||
| **Mentioned during lecture:** | **Mentioned during lecture:** | ||
| - | * {{bstj29-2-147.pdf|Hamming, R. W. (1950). Error Detecting and Error Correcting Codes. Bell System Technical Journal, 29(2).}} | + | ===== Lecture 2 (1/14 Wed.) ===== |
| - | * {{youandyourresearch.pdf|Hamming, R. W. (1986). You and Your Research. Transcription of the Bell Communications Research Colloquium Seminar.}} | + | |
| - | * [[http://www.youtube.com/watch?v=a1zDuOPkMSw|youtube]] | + | |
| - | * {{05392210.pdf|Amdahl, G. M., Blaauw, G. A., & Brooks, F. P. (1964). Architecture of the IBM system/360. IBM J. Res. Dev., 8(2).}} | + | |
| - | * {{p128-rixner.pdf|Rixner, S., Dally, W. J., Kapasi, U. J., Mattson, P., & Owens, J. D. (2000). Memory access scheduling. Proceedings of the 27th annual international symposium on Computer architecture.}} | + | |
| - | * {{us5630096.pdf|William K. Zuravleff, & Robinson, T. (1997). Controller for a synchronous DRAM that maximizes throughput by allowing memory requests and commands to be issued out of order.}} | + | |
| - | * {{00964437.pdf|Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.}} | + | |
| - | * {{moscibroda.pdf|Moscibroda, T., & Mutlu, O. (2007). Memory performance attacks: denial of memory service in multi-core systems. Proceedings of 16th USENIX Security Symposium.}} | + | |
| - | + | ||
| - | ===== Lecture 2 (1/15 Wed.) ===== | + | |
| **Required:** | **Required:** | ||
| * {{00964437.pdf|Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.}} | * {{00964437.pdf|Patt, Y. (2001). Requirements, bottlenecks, and good fortune: agents for microprocessor evolution. Proceedings of the IEEE.}} | ||
| Line 25: | Line 20: | ||
| * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/PP_Chap1.pdf|P&P Chapter 1 (Fundamentals)]] | * (CMU WebISO) [[http://www.ece.cmu.edu/~ece447/cmu_only/PP_Chap1.pdf|P&P Chapter 1 (Fundamentals)]] | ||
| * P&H Chapters 1 and 2 (Intro, Abstractions, ISA, MIPS) | * P&H Chapters 1 and 2 (Intro, Abstractions, ISA, MIPS) | ||
| - | * | + | |
| + | |||
| + | **Mentioned during lecture:** | ||
| + | |||
readings.txt · Last modified: 2015/04/13 19:31 by kevincha
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