labs
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labs [2014/12/20 21:25] kevincha |
labs [2015/02/09 20:19] jeremie [Lab 3: Pipelined MIPS (Due: Fri. 2/20)] |
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| ===== Lab 1: Instruction Level MIPS Simulator (Due: Fri. 1/23) ===== | ===== Lab 1: Instruction Level MIPS Simulator (Due: Fri. 1/23) ===== | ||
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| + | * [[https://milkshark.ics.cs.cmu.edu/courses/25/assessments/11 | Autolab]] | ||
| + | * {{lab1-handout.tar}} | ||
| + | * {{lab1_grade_447.pdf|Grade distribution}} | ||
| ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ||
| - | ===== Lab 2: Single Cycle MIPS (Due: Fri. 2/6)===== | + | * {{lab1.5.pdf|Lab 1.5 Handout}} |
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| - | ===== Lab 3: Pipelining (Due: Fri. 2/20)===== | + | |
| - | + | ||
| - | ===== Lab 4a: Branch Prediction (Due: Fri. 3/20)===== | + | |
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| - | ===== Lab 4b: TBD (Due: Fri. 3/20) ===== | + | |
| - | ===== Lab 5: Simulating Caches and Branch Prediction (Due: Fri. 4/3)===== | + | ===== Lab 2: Instruction Level MIPS Simulator (Due: Fri. 2/6) ===== |
| - | ===== Lab 6: Memory Hierarchy (Due: Fri. 4/17)===== | + | * {{lab2-handout.tar}} |
| + | * {{lab2.pdf}} | ||
| - | ===== Lab 7: Multicore and Cache Coherence (Due: Fri. 5/1)===== | + | ==== Lab 3: Pipelined MIPS (Due: Fri. 2/20) ===== |
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| + | * [[https://milkshark.ics.cs.cmu.edu/courses/25/assessments/197 | Autolab]] | ||
labs.txt · Last modified: 2017/09/17 00:10 by jeremie
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