labs
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labs [2014/04/18 19:00] rachata |
labs [2014/11/26 19:06] rachata |
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| * {{lab1.tar|Lab 1 Starter Code}} | * {{lab1.tar|Lab 1 Starter Code}} | ||
| * {{lab1_dist.pdf|Lab 1 Grade Distribution}} | * {{lab1_dist.pdf|Lab 1 Grade Distribution}} | ||
| + | * {{arm2hex.tar| arm2hex}} | ||
| + | |||
| ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ||
| Line 26: | Line 28: | ||
| * {{lab4.pdf|Lab 4a Handout}} | * {{lab4.pdf|Lab 4a Handout}} | ||
| + | * {{lab4_dist.pdf|Lab 4 Grade Distribution}} | ||
| ===== Lab 4b: Fine-Grained Multithreading (Due: Fri. 3/21)===== | ===== Lab 4b: Fine-Grained Multithreading (Due: Fri. 3/21)===== | ||
| * {{lab4b.pdf|Lab 4b Handout}} | * {{lab4b.pdf|Lab 4b Handout}} | ||
| + | * {{lab4_dist.pdf|Lab 4 Grade Distribution}} | ||
| ===== Lab 5: Simulating Caches and Branch Prediction (Due: Sun. 4/6)===== | ===== Lab 5: Simulating Caches and Branch Prediction (Due: Sun. 4/6)===== | ||
| Line 36: | Line 40: | ||
| * {{lab5_starter.tar.gz|Lab 5 Starter Code}} | * {{lab5_starter.tar.gz|Lab 5 Starter Code}} | ||
| * [[lab5_faq|Lab 5 FAQs]] | * [[lab5_faq|Lab 5 FAQs]] | ||
| + | * {{lab5_dist.pdf|Lab 5 Grade Distribution}} | ||
| ===== Lab 6: Memory Hierarchy (Due: Sun. 4/20)===== | ===== Lab 6: Memory Hierarchy (Due: Sun. 4/20)===== | ||
| * {{lab6.pdf|Lab 6 Handout}} | * {{lab6.pdf|Lab 6 Handout}} | ||
| + | * {{lab6_dist.pdf|Lab 6 Grade Distribution}} | ||
| ===== Lab 7: Multicore and Cache Coherence (Due: Fri. 5/2)===== | ===== Lab 7: Multicore and Cache Coherence (Due: Fri. 5/2)===== | ||
| + | * (Accept late submissions until May 9) | ||
| * {{lab7.pdf|Lab 7 Handout}} | * {{lab7.pdf|Lab 7 Handout}} | ||
labs.txt · Last modified: 2017/09/17 00:10 by jeremie
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