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--- labs [2014/02/24 06:19]
xiao [Lab 4a: Branch Prediction (Due: Fri. 3/21)]
+++ labs [2014/12/20 21:25]
kevincha
@@ Line 3: / Line 3: @@
 ====== Labs ======
-===== Lab 1: Instruction Level ARM Simulator (Due: Fri. 1/24) =====
+===== Lab 1: Instruction Level MIPS Simulator (Due: Fri. 1/23) =====
-  * {{lab1.pdf|Lab 1 Handout}}
-  * {{lab1.tar|Lab 1 Starter Code}}
-  * {{lab1_dist.pdf|Lab 1 Grade Distribution}}
 ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) =====
-  * {{lab1.5.pdf|Lab 1.5 Handout}}
+===== Lab 2: Single Cycle MIPS (Due: Fri. 2/6)=====
-===== Lab 2: Single Cycle ARM (Due: Fri. 2/7)=====
+===== Lab 3: Pipelining (Due: Fri. 2/20)=====
-  * {{lab2.pdf|Lab 2 Handout}}
+===== Lab 4a: Branch Prediction (Due: Fri. 3/20)=====
-  * {{lab2.tar.gz|Lab 2 Starter Code}}
-  * {{lab2_dist.pdf|Lab 2 Grade Distribution}}
-===== Lab 3: Pipelining (Due: Fri. 2/21)=====
+===== Lab 4b: TBD (Due: Fri. 3/20) =====
-  * {{lab3.pdf|Lab 3 Handout}}
+===== Lab 5: Simulating Caches and Branch Prediction (Due: Fri. 4/3)=====
-===== Lab 4a: Branch Prediction (Due: Fri. 3/21)=====
-  * {{lab4.pdf|Lab 4a Handout}}
-===== Lab 4b: Fine-Grained Multithreading (Due: Fri. 3/21)=====
-  * {{lab4b.pdf|Lab 4b Handout}}
+===== Lab 6: Memory Hierarchy (Due: Fri. 4/17)=====
+===== Lab 7: Multicore and Cache Coherence (Due: Fri. 5/1)=====

18-447 Introduction to Computer Architecture – Spring 2015