This shows you the differences between two versions of the page.
Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
labs [2014/01/29 20:59] varun [Lab 2: Single Cycle ARM (Due: Fri. 2/7)] |
labs [2015/04/24 19:15] onur [Lab 7: Memory Hierarchy (Due: Fri. 04/17)] |
||
---|---|---|---|
Line 3: | Line 3: | ||
====== Labs ====== | ====== Labs ====== | ||
- | ===== Lab 1: Instruction Level ARM Simulator (Due: Fri. 1/24) ===== | + | ===== Lab 1: Instruction Level MIPS Simulator (Due: Fri. 1/23) ===== |
- | + | ||
- | * {{lab1.pdf|Lab 1 Handout}} | + | * [[https://milkshark.ics.cs.cmu.edu/courses/25/assessments/11 | Autolab]] |
- | * {{lab1.tar|Lab 1 Starter Code}} | + | * {{lab1-handout.tar}} |
+ | * {{lab1.pdf|Handout}} | ||
+ | * {{lab1_grade_447.pdf|Grade distribution}} | ||
===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ||
- | * {{lab1.5.pdf|Lab 1.5 Handout}} | + | * {{lab1.5.pdf|Lab 1.5 Handout}} |
+ | |||
+ | ===== Lab 2: Instruction Level MIPS Simulator (Due: Fri. 2/6) ===== | ||
+ | |||
+ | * {{lab2-handout.tar}} | ||
+ | * {{lab2.pdf}} | ||
+ | * {{lab2_grade_dist.pdf|Grade distribution}} | ||
+ | ===== Lab 3: Pipelined MIPS (Due: Fri. 2/20) ===== | ||
+ | |||
+ | * [[https://milkshark.ics.cs.cmu.edu/courses/25/assessments/197 | Autolab]] | ||
+ | * {{lab3.pdf|Handout}} | ||
+ | * {{lab3-handout.tar}} | ||
+ | * {{lab3_grade_dist.pdf|Grade distribution}} | ||
+ | ===== Lab 4: Branch Prediction (Due: Fri. 03/06) ===== | ||
+ | |||
+ | * [[https://autolab.cs.cmu.edu/courses/25/assessments/347 | Autolab]] | ||
+ | * {{lab4.pdf|Handout}} | ||
+ | * {{lab4.tar.gz}} | ||
+ | * {{lab4_grade_dist.pdf|Grade distribution}} | ||
+ | ===== Lab 5: Data Cache (Due: Sun. 03/22) ===== | ||
+ | |||
+ | * [[https://autolab.cs.cmu.edu/courses/25/assessments/377 | Autolab]] | ||
+ | * {{lab5.pdf|Handout}} | ||
+ | * {{lab5.tar.gz}} | ||
+ | * {{lab5_dist.pdf|Grade distribution}} | ||
+ | ===== Lab 6: Simulating Caches and Branch Prediction (Due: Fri. 04/03) ===== | ||
+ | |||
+ | * [[https://autolab.cs.cmu.edu/courses/25/assessments/476 | Autolab]] | ||
+ | * {{lab6.pdf|Handout}} | ||
+ | * {{lab6.tar.gz}} | ||
+ | * {{lab6_grade_dist.pdf|Grade distribution}} | ||
+ | |||
+ | ===== Lab 7: Memory Hierarchy (Due: Fri. 04/17, but can submit until 5/1) ===== | ||
+ | |||
+ | * [[https://autolab.cs.cmu.edu/courses/18447-s15/assessments/lab7 | Autolab]] | ||
+ | * {{lab7.pdf|Handout}} | ||
- | ===== Lab 2: Single Cycle ARM (Due: Fri. 2/7)===== | + | ===== Lab 8: Multicore and Cache Coherence (Due: Sun. 5/3) ===== |
- | * {{lab2.pdf|Lab 2 Handout}} | + | * [[https://autolab.cs.cmu.edu/courses/18447-s15/assessments/lab8 | Autolab]] |
- | * {{lab2.tar.gz|Lab 2 Starter Code}} | + | * {{lab8.pdf|Handout}} |
+ | * {{lab8.tar.gz}} |