labs
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labs [2014/01/29 20:59] varun [Lab 2: Single Cycle ARM (Due: Fri. 2/7)] |
labs [2014/12/20 21:25] kevincha |
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| ====== Labs ====== | ====== Labs ====== | ||
| - | ===== Lab 1: Instruction Level ARM Simulator (Due: Fri. 1/24) ===== | + | ===== Lab 1: Instruction Level MIPS Simulator (Due: Fri. 1/23) ===== |
| - | * {{lab1.pdf|Lab 1 Handout}} | ||
| - | * {{lab1.tar|Lab 1 Starter Code}} | ||
| ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ||
| - | * {{lab1.5.pdf|Lab 1.5 Handout}} | + | ===== Lab 2: Single Cycle MIPS (Due: Fri. 2/6)===== |
| - | ===== Lab 2: Single Cycle ARM (Due: Fri. 2/7)===== | + | ===== Lab 3: Pipelining (Due: Fri. 2/20)===== |
| - | * {{lab2.pdf|Lab 2 Handout}} | + | ===== Lab 4a: Branch Prediction (Due: Fri. 3/20)===== |
| - | * {{lab2.tar.gz|Lab 2 Starter Code}} | + | |
| + | ===== Lab 4b: TBD (Due: Fri. 3/20) ===== | ||
| + | |||
| + | ===== Lab 5: Simulating Caches and Branch Prediction (Due: Fri. 4/3)===== | ||
| + | |||
| + | ===== Lab 6: Memory Hierarchy (Due: Fri. 4/17)===== | ||
| + | |||
| + | ===== Lab 7: Multicore and Cache Coherence (Due: Fri. 5/1)===== | ||
labs.txt · Last modified: 2017/09/17 00:10 by jeremie
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