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labs [2014/01/29 20:50] varun [Lab 2: Single Cycle ARM] |
labs [2014/04/04 06:48] rachata |
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* {{lab1.pdf|Lab 1 Handout}} | * {{lab1.pdf|Lab 1 Handout}} | ||
+ | * {{lab1.tar|Lab 1 Starter Code}} | ||
+ | * {{lab1_dist.pdf|Lab 1 Grade Distribution}} | ||
===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ||
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* {{lab2.pdf|Lab 2 Handout}} | * {{lab2.pdf|Lab 2 Handout}} | ||
+ | * {{lab2.tar.gz|Lab 2 Starter Code}} | ||
+ | * {{lab2_dist.pdf|Lab 2 Grade Distribution}} | ||
+ | |||
+ | ===== Lab 3: Pipelining (Due: Fri. 2/21)===== | ||
+ | |||
+ | * {{lab3.pdf|Lab 3 Handout}} | ||
+ | * {{lab3_grades.pdf|Lab 3 Grade Distribution}} | ||
+ | |||
+ | ===== Lab 4a: Branch Prediction (Due: Fri. 3/21)===== | ||
+ | |||
+ | * {{lab4.pdf|Lab 4a Handout}} | ||
+ | |||
+ | ===== Lab 4b: Fine-Grained Multithreading (Due: Fri. 3/21)===== | ||
+ | |||
+ | * {{lab4b.pdf|Lab 4b Handout}} | ||
+ | |||
+ | ===== Lab 5: Simulating Caches and Branch Prediction (Due: Sun. 4/6)===== | ||
+ | |||
+ | * {{lab5.pdf|Lab 5 Handout}} | ||
+ | * {{lab5_starter.tar.gz|Lab 5 Starter Code}} | ||
+ | * [[lab5_faq|Lab 5 FAQs]] | ||
+ | * | ||
+ | ===== Lab 6: Memory Hierarchy (Due: Sun. 4/18)===== | ||
+ | |||
+ | * {{lab6.pdf|Lab 6 Handout}} |