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labs [2014/01/22 04:32] varun [Lab 1: Instruction Level ARM Simulator (Due: Fri. 1/24)] |
labs [2014/01/29 20:59] varun [Lab 2: Single Cycle ARM (Due: Fri. 2/7)] |
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* {{lab1.pdf|Lab 1 Handout}} | * {{lab1.pdf|Lab 1 Handout}} | ||
+ | * {{lab1.tar|Lab 1 Starter Code}} | ||
===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ||
* {{lab1.5.pdf|Lab 1.5 Handout}} | * {{lab1.5.pdf|Lab 1.5 Handout}} | ||
+ | ===== Lab 2: Single Cycle ARM (Due: Fri. 2/7)===== | ||
+ | |||
+ | * {{lab2.pdf|Lab 2 Handout}} | ||
+ | * {{lab2.tar.gz|Lab 2 Starter Code}} |