This shows you the differences between two versions of the page.
Next revision | Previous revision Next revision Both sides next revision | ||
labs [2014/01/15 20:37] varun created |
labs [2014/12/11 00:09] 127.0.0.1 external edit |
||
---|---|---|---|
Line 6: | Line 6: | ||
* {{lab1.pdf|Lab 1 Handout}} | * {{lab1.pdf|Lab 1 Handout}} | ||
+ | * {{lab1.tar|Lab 1 Starter Code}} | ||
+ | * {{lab1_dist.pdf|Lab 1 Grade Distribution}} | ||
+ | * {{arm2hex.tar| arm2hex}} | ||
+ | ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ||
+ | |||
+ | * {{lab1.5.pdf|Lab 1.5 Handout}} | ||
+ | |||
+ | ===== Lab 2: Single Cycle ARM (Due: Fri. 2/7)===== | ||
+ | |||
+ | * {{lab2.pdf|Lab 2 Handout}} | ||
+ | * {{lab2.tar.gz|Lab 2 Starter Code}} | ||
+ | * {{lab2_dist.pdf|Lab 2 Grade Distribution}} | ||
+ | |||
+ | ===== Lab 3: Pipelining (Due: Fri. 2/21)===== | ||
+ | |||
+ | * {{lab3.pdf|Lab 3 Handout}} | ||
+ | * {{lab3_grades.pdf|Lab 3 Grade Distribution}} | ||
+ | |||
+ | ===== Lab 4a: Branch Prediction (Due: Fri. 3/21)===== | ||
+ | |||
+ | * {{lab4.pdf|Lab 4a Handout}} | ||
+ | * {{lab4_dist.pdf|Lab 4 Grade Distribution}} | ||
+ | |||
+ | ===== Lab 4b: Fine-Grained Multithreading (Due: Fri. 3/21)===== | ||
+ | |||
+ | * {{lab4b.pdf|Lab 4b Handout}} | ||
+ | * {{lab4_dist.pdf|Lab 4 Grade Distribution}} | ||
+ | |||
+ | ===== Lab 5: Simulating Caches and Branch Prediction (Due: Sun. 4/6)===== | ||
+ | |||
+ | * {{lab5.pdf|Lab 5 Handout}} | ||
+ | * {{lab5_starter.tar.gz|Lab 5 Starter Code}} | ||
+ | * [[lab5_faq|Lab 5 FAQs]] | ||
+ | * {{lab5_dist.pdf|Lab 5 Grade Distribution}} | ||
+ | |||
+ | ===== Lab 6: Memory Hierarchy (Due: Sun. 4/20)===== | ||
+ | |||
+ | * {{lab6.pdf|Lab 6 Handout}} | ||
+ | * {{lab6_dist.pdf|Lab 6 Grade Distribution}} | ||
+ | |||
+ | ===== Lab 7: Multicore and Cache Coherence (Due: Fri. 5/2)===== | ||
+ | |||
+ | * (Accept late submissions until May 9) | ||
+ | * {{lab7.pdf|Lab 7 Handout}} |