labs
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labs [2014/01/15 20:37] varun created |
labs [2014/02/19 17:44] rachata |
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| * {{lab1.pdf|Lab 1 Handout}} | * {{lab1.pdf|Lab 1 Handout}} | ||
| + | * {{lab1.tar|Lab 1 Starter Code}} | ||
| + | * {{lab1_dist.pdf|Lab 1 Grade Distribution}} | ||
| + | ===== Lab 1.5: SystemVerilog Warm-Up (Due: Never) ===== | ||
| + | |||
| + | * {{lab1.5.pdf|Lab 1.5 Handout}} | ||
| + | |||
| + | ===== Lab 2: Single Cycle ARM (Due: Fri. 2/7)===== | ||
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| + | * {{lab2.pdf|Lab 2 Handout}} | ||
| + | * {{lab2.tar.gz|Lab 2 Starter Code}} | ||
| + | * {{lab2_dist.pdf|Lab 2 Grade Distribution}} | ||
| + | |||
| + | ===== Lab 3: Pipelining (Due: Fri. 2/21)===== | ||
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| + | * {{lab3.pdf|Lab 3 Handout}} | ||
labs.txt · Last modified: 2017/09/17 00:10 by jeremie
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