buzzword
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buzzword [2015/04/01 18:17] rachata |
buzzword [2015/04/03 18:20] rachata |
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| * How much did the prefetcher cause misses in the demand misses? | * How much did the prefetcher cause misses in the demand misses? | ||
| * Hard to quantify | * Hard to quantify | ||
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| + | ===== Lecture 26 (4/3 Fri.) ===== | ||
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| + | * Feedback directed prefetcher | ||
| + | * Use the result of the prefetcher as a feedback to the prefetcher | ||
| + | * with accuracy, timeliness, polluting information | ||
| + | * Markov prefetcher | ||
| + | * Prefetch based on the previous history | ||
| + | * Use markov model to predict | ||
| + | * Pros: Can cover arbitary pattern (easy for link list traversal or trees) | ||
| + | * Downside: High cost, cannot help with compulsory misses (no history) | ||
| + | * Content directed prefetching | ||
| + | * Indentify the content in memory for pointers (which is used as the address to prefetch | ||
| + | * Not very efficient (hard to figure out which block is the pointer) | ||
| + | * Software can give hints | ||
| + | * Correlation table | ||
| + | * Address correlation | ||
| + | * Execution based prefetcher | ||
| + | * Helper thread/speculative thread | ||
| + | * Use another thread to pre-execute a program | ||
| + | * Can be a software based or hardware based | ||
| + | * Discover misses before the main program (to prefetch data in a timely manner) | ||
| + | * How do you construct the helper thread | ||
| + | * Preexecute instruction (one example of how to initialize a speculative thread), slide 9 | ||
| + | * Thread-based pre-execution | ||
| + | * Error tolerance | ||
| + | * Solution to errors | ||
| + | * Tolerate errors | ||
| + | * New interface, new design | ||
| + | * Eliminate or minimize errors | ||
| + | * New technology, system-wide rethinking | ||
| + | * Embrace errors | ||
| + | * Map data that can tolerate errors to error-prone area | ||
| + | * Hybrid memory systesm | ||
| + | * Combining multiple memory technology together | ||
| + | * What can emerging technology help? | ||
| + | * Scalability | ||
| + | * Lower the cost | ||
| + | * Energy efficiency | ||
| + | * Possible solutions to the scaling problem | ||
| + | * Less leakage DRAM | ||
| + | * Heterogeneous DRAM (TL-DRAM, etc.) | ||
| + | * Add more functionality to DRAM | ||
| + | * Denser design (3D stack) | ||
| + | * Different technology | ||
| + | * NVM | ||
| + | * Charge vs. resistice memory | ||
| + | * How data is written? | ||
| + | * How to read the data? | ||
| + | * Non volatile memory | ||
| + | * Resistive memory | ||
| + | * PCM | ||
| + | * Inject current to change the phase | ||
| + | * Scales better than DRAM | ||
| + | * Multiple bits per cell | ||
| + | * Wider resistence range | ||
| + | * No refresh is needed | ||
| + | * Downside: Latency and write endurance | ||
| + | * STT-MRAM | ||
| + | * Inject current to change the polarity | ||
| + | * Memristor | ||
| + | * Inject current to change the structure | ||
| + | * Pros and cons between different technologies | ||
| + | * Persistency - data stay there even without power | ||
| + | * Unified memory and storage management (persistent data structure) - Single level store | ||
| + | * Improve energy and performance | ||
| + | * Simplify programming model | ||
| + | * Different design options for DRAM + NVM | ||
| + | * DRAM as a cache | ||
| + | * Place some data in DRAM and other in PCM | ||
| + | * Based on the characteristics | ||
| + | * Frequently accessed data that need lower write latency in DRAM | ||
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buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
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