buzzword
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buzzword [2015/03/25 18:19] rachata |
buzzword [2015/03/30 23:15] rachata |
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| + | ===== Lecture 23 (03/27 Fri.) ===== | ||
| + | |||
| + | * Different ways to control interference in DRAM | ||
| + | * Partitioning of resource | ||
| + | * Channel partitioning: map applications that interfere with each other in a different channel | ||
| + | * Keep track of application's characteristics | ||
| + | * Dedicate a channel might waste the bandwidth | ||
| + | * Need OS support to determine the channel bits | ||
| + | * Source throttling | ||
| + | * A controller throttle the core depends on the performance target | ||
| + | * Example: Fairness via source throttling | ||
| + | * Detect unfairness and throttle application that is interfering | ||
| + | * How do you estimate slowdown? | ||
| + | * Threshold based solution: hard to configure | ||
| + | * App/thread scheduling | ||
| + | * Critical threads usually stall the progress | ||
| + | * Designing DRAM controller | ||
| + | * Has to handle the normal DRAM operations | ||
| + | * Read/write/refresh/all the timing constraints | ||
| + | * Keep track of resources | ||
| + | * Assign priorities to different requests | ||
| + | * Manage requests to banks | ||
| + | * Self-optimizing controller | ||
| + | * Use machine learning to improve DRAM controller | ||
| + | * A-DRM | ||
| + | * Architecture aware DRAM | ||
| + | * Multithread | ||
| + | * synchronization | ||
| + | * Pipeline programs | ||
| + | * Producer consumer model | ||
| + | * Critical path | ||
| + | * Limiter threads | ||
| + | * Prioritization between threads | ||
| + | * Different power mode in DRAM | ||
| + | * DRAM Refresh | ||
| + | * Why does DRAM has to refresh every 64ms | ||
| + | * Banks are unavailable during refresh | ||
| + | * LPDDR mitigate this by using a per-bank refresh | ||
| + | * Has to spend longer time with bigger DRAM | ||
| + | * Distributed refresh: stagger refresh every 64 ms in a distributed manner | ||
| + | * As oppose to burst refresh (long pause time) | ||
| + | * RAIDR: Reduce DRAM refresh by profiling and binning | ||
| + | * Some row do not have to be refresh very frequently | ||
| + | * Profile the row | ||
| + | * High temperature changes the retention time: need online profiling | ||
| + | * Bloom filter | ||
| + | * Represent set membership | ||
| + | * Approximated | ||
| + | * Can contain false positive | ||
| + | * Better/more hash function helps eliminate this | ||
| | | ||
| + | ===== Lecture 24 (03/30 Mon.) ===== | ||
| + | |||
| + | * Simulation | ||
| + | * Drawbacks of RTL simulations | ||
| + | * Time consuming | ||
| + | * Complex to develop | ||
| + | * Hard to perform design explorations | ||
| + | * Explore the design space quickly | ||
| + | * Match the behavior of existing systems | ||
| + | * Tradeoffs: speed, accuracy, flexibility | ||
| + | * High-level simulation vs. detailed simulation | ||
| + | * High-level simulation is faster, but lower accuracy | ||
| + | * Controllers that works on multiple types of cores | ||
| + | * Design problems: how to find a good scheduling policy on its own? | ||
| + | * Self-optimizing memory controller: using machine learning | ||
| + | * Can adapt to the applications | ||
| + | * The complexity is very high | ||
| + | * Tolerate latency can be costly | ||
| + | * Instruction window is complex | ||
| + | * Benefit also diminishes | ||
| + | * Designing the buffers can be complex | ||
| + | * A simpler way to tolerate out of order is desirable | ||
| + | * Different sources that cause the core to stall in OoO | ||
| + | * Cache miss | ||
| + | * Note that stall happens if the inst. window is full | ||
| + | * Scaling instruction window size is hard | ||
| + | * It is better (less complex) to make the windows more efficient | ||
| + | * Runahead execution | ||
| + | * Try to optain MLP w/o increasing instruction windows | ||
| + | * Runahead (i.e. execute ahead) when there is a long memory instruction | ||
| + | * Long memory instruction stall processor for a while anyways, so it's better to make use out of it | ||
| + | * Execute future instruction to generate accurate prefetches | ||
| + | * Allow future data to be in the cache | ||
| + | * How to support runahead execution? | ||
| + | * Need a way to checkpoing the state when entering runahead mode | ||
| + | * How to make executing in the wrong path useful? | ||
| + | * Need runahead cache to handle load/store in Runahead mode (since they are speculative) | ||
| + | |||
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
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