buzzword
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision | Next revision Both sides next revision | ||
|
buzzword [2015/03/23 18:02] rachata |
buzzword [2015/03/25 18:19] rachata |
||
|---|---|---|---|
| Line 873: | Line 873: | ||
| * Send requests whenever the request can be sent to the bank | * Send requests whenever the request can be sent to the bank | ||
| * Determine which command (across banks) should be sent to DRAM | * Determine which command (across banks) should be sent to DRAM | ||
| + | |||
| + | ===== Lecture 22 (03/25 Wed.) ===== | ||
| + | |||
| + | |||
| + | |||
| + | * Flash controller | ||
| + | * Flash memory | ||
| + | * Garbage collection in flash | ||
| + | * Overhead in flash memory | ||
| + | * Erase (off the critical path, but takes a long time) | ||
| + | * Different types of DRAM | ||
| + | * DRAM design choices | ||
| + | * Cost/density/latency/BW/Yield | ||
| + | * Sense Amplifier | ||
| + | * How do they work | ||
| + | * Dual data rate | ||
| + | * Subarray | ||
| + | * Rowclone | ||
| + | * Moving bulk of data from one row to others | ||
| + | * Lower latency and BW when performing copies/zeroes out the data | ||
| + | * TL-DRAM | ||
| + | * Far segment | ||
| + | * Near segment | ||
| + | * What causes the long latency | ||
| + | * Benefit of TL-DRAM | ||
| + | * TL-DRAM vs. DRAM cache (adding a small cache in DRAM) | ||
| + | * List of commands to read/write data into DRAM | ||
| + | * Activate -> read/write -> precharge | ||
| + | * Activate moves data into the row buffer | ||
| + | * Precharge prepare the bank for the next access | ||
| + | * Row buffer hit | ||
| + | * Row buffer conflict | ||
| + | * Scheduling memory requests to lower row conflicts | ||
| + | * Burst mode of DRAM | ||
| + | * Prefetch 32-bits from an 8-bit interface if DRAM needs to read 32 bits | ||
| + | * Address mapping | ||
| + | * Row interleaved | ||
| + | * Cache block interleaved | ||
| + | * Memory controller | ||
| + | * Sending DRAM commands | ||
| + | * Periodically send commands to refresh DRAM cells | ||
| + | * Ensure correctness and data integrity | ||
| + | * Where to place the memory controller | ||
| + | * On CPU chip vs. at the main memory | ||
| + | * Higher BW on-chip | ||
| + | * Determine the order of requests that will be serviced in DRAM | ||
| + | * Request queues that hold requests | ||
| + | * Send requests whenever the request can be sent to the bank | ||
| + | * Determine which command (across banks) should be sent to DRAM | ||
| + | * Priority of demand vs. prefetch requests | ||
| + | * Memory scheduling policies | ||
| + | * FCFS | ||
| + | * FR-FCFS | ||
| + | * Try to maximize row buffer hit rate | ||
| + | * Capped FR-FCFS: FR-FCFS with a timeout | ||
| + | * Usually this is done in a command level (read/write commands and precharge/activate commands) | ||
| + | * PAR-BS | ||
| + | * Key benefits | ||
| + | * stall time | ||
| + | * shortest job first | ||
| + | * STFM | ||
| + | * ATLAS | ||
| + | * TCM | ||
| + | * Key benefits | ||
| + | * Configurability | ||
| + | * Fairness + performance at the same time | ||
| + | * Robuestness isuees | ||
| + | * Open row policy | ||
| + | * Closed row policy | ||
| + | * QoS | ||
| + | * QoS issues in memory scheduling | ||
| + | * Fairness | ||
| + | * Performance guarantee | ||
| + | |||
| | | ||
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
