buzzword
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buzzword [2015/03/17 02:29] kevincha |
buzzword [2015/03/23 18:02] rachata |
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| * Page coloring | * Page coloring | ||
| * Interaction between cache and TLB | * Interaction between cache and TLB | ||
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| + | ===== Lecture 21 (03/23 Mon.) ===== | ||
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| + | * DRAM scaling problem | ||
| + | * Demands/trends affecting the main memory | ||
| + | * More capacity | ||
| + | * Low energy | ||
| + | * More bandwidth | ||
| + | * QoS | ||
| + | * ECC in DRAM | ||
| + | * Multi-porting | ||
| + | * Virtual multi-porting | ||
| + | * Time-share the port, not too scalable but cheap | ||
| + | * True multiporting | ||
| + | * Multiple cache copies | ||
| + | * Alignment | ||
| + | * Banking | ||
| + | * Can have bank conflict | ||
| + | * Extra interconnects across banks | ||
| + | * Address mapping can mitigate bank conflict | ||
| + | * Common in main memory (note that regFile in GPU is also banked, but mainly for the pupose of reducing complexity) | ||
| + | * Bank mapping | ||
| + | * How to avoid bank conflicts? | ||
| + | * Channel mapping | ||
| + | * Address mapping to minimize bank conflict | ||
| + | * Page coloring | ||
| + | * Virtual to physical mapping that can help reducing conflicts | ||
| + | * Accessing DRAM | ||
| + | * Row bits | ||
| + | * Column bits | ||
| + | * Addressibility | ||
| + | * DRAM has its own clock | ||
| + | * Sense amplifier | ||
| + | * Bit lines | ||
| + | * Word lines | ||
| + | * DRAM (2T) vs. SRAM (6T) | ||
| + | * Cost | ||
| + | * Latency | ||
| + | * Interleaving in DRAM | ||
| + | * Effects from address mapping on memory interleaving | ||
| + | * Effects from memory access patterns from the program on interleaving | ||
| + | * DRAM Bank | ||
| + | * To minimize the cost of interleaving (Shared the data bus and the command bus) | ||
| + | * DRAM Rank | ||
| + | * Minimize the cost of the chip (a bundle of chips operated together) | ||
| + | * DRAM Channel | ||
| + | * An interface to DRAM, each with its own ranks/banks | ||
| + | * DRAM Chip | ||
| + | * DIMM | ||
| + | * More DIMM adds the interconnect complexity | ||
| + | * List of commands to read/write data into DRAM | ||
| + | * Activate -> read/write -> precharge | ||
| + | * Activate moves data into the row buffer | ||
| + | * Precharge prepare the bank for the next access | ||
| + | * Row buffer hit | ||
| + | * Row buffer conflict | ||
| + | * Scheduling memory requests to lower row conflicts | ||
| + | * Burst mode of DRAM | ||
| + | * Prefetch 32-bits from an 8-bit interface if DRAM needs to read 32 bits | ||
| + | * Address mapping | ||
| + | * Row interleaved | ||
| + | * Cache block interleaved | ||
| + | * Memory controller | ||
| + | * Sending DRAM commands | ||
| + | * Periodically send commands to refresh DRAM cells | ||
| + | * Ensure correctness and data integrity | ||
| + | * Where to place the memory controller | ||
| + | * On CPU chip vs. at the main memory | ||
| + | * Higher BW on-chip | ||
| + | * Determine the order of requests that will be serviced in DRAM | ||
| + | * Request queues that hold requests | ||
| + | * Send requests whenever the request can be sent to the bank | ||
| + | * Determine which command (across banks) should be sent to DRAM | ||
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buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
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