buzzword
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision | Next revision Both sides next revision | ||
|
buzzword [2015/02/16 19:16] rachata |
buzzword [2015/02/18 19:22] rachata |
||
|---|---|---|---|
| Line 522: | Line 522: | ||
| * Difficulties? | * Difficulties? | ||
| + | ===== Lecture 14 (2/18 Wed.) ===== | ||
| + | |||
| + | * SISD/SIMD/MISD/MIMD | ||
| + | * Array processor | ||
| + | * Vector processor | ||
| + | * Data parallelism | ||
| + | * Where does the concurrency arise? | ||
| + | * Differences between array processor vs. vector processor | ||
| + | * VLIW | ||
| + | * Compactness of an array processor | ||
| + | * Vector operates on a vector of data (rather than a single datum (scalar)) | ||
| + | * Vector length (also applies to array processor) | ||
| + | * No dependency within a vector --> can have a deep pipeline | ||
| + | * Highly parallel (both instruction level (ILP) and memory level (MLP)) | ||
| + | * But the program needs to be very parallel | ||
| + | * Memory can be the bottleneck (due to very high MLP) | ||
| + | * What does the functional units look like? Deep pipelin and simpler control. | ||
| + | * CRAY-I is one of the examples of vector processor | ||
| + | * Memory access pattern in a vector processor | ||
| + | * How do the memory accesses benefit the memory bandwidth? | ||
| + | * Memory level parallelism | ||
| + | * Stride length vs. the number of banks | ||
| + | * stride length should be relatively prime to the number of banks | ||
| + | * Tradeoffs between row major and column major --> How can the vector processor deals with the two | ||
| + | * How to calculate the efficiency and performance of vector processors | ||
| + | * What if there are multiple memory ports? | ||
| + | * Gather/Scatter allows vector processor to be a lot more programmable (i.e. gather data for parallelism) | ||
| + | * Helps handling sparse metrices | ||
| + | * Conditional operation | ||
| + | * Structure of vector units | ||
| + | * How to automatically parallelize code through the compiler? | ||
| + | * This is a hard problem. Compiler does not know the memory address. | ||
| + | * What do we need to ensure for both vector and array processor? | ||
| + | * Sequential bottleneck | ||
| + | * Amdahl's law | ||
| + | * Intel MMX --> An example of Intel's approach to SIMD | ||
| + | * No VLEN, use OpCode to define the length | ||
| + | * Stride is one in MMX | ||
| + | * Intel SSE --> Modern version of MMX | ||
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
