buzzword
Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
|
buzzword [2015/01/30 19:24] rachata |
buzzword [2015/02/25 21:05] kevincha [Lecture 17 (2/25 Wed.)] |
||
|---|---|---|---|
| Line 243: | Line 243: | ||
| * Primitives | * Primitives | ||
| | | ||
| - | ===== Lecture 7 (1/30 Mon.) ===== | + | ===== Lecture 7 (1/30 Fri.) ===== |
| * Emulator (i.e. uCode allots minimal datapath to emulate the ISA) | * Emulator (i.e. uCode allots minimal datapath to emulate the ISA) | ||
| Line 277: | Line 277: | ||
| * Pipeline flush | * Pipeline flush | ||
| * Speculation | * Speculation | ||
| + | | ||
| + | ===== Lecture 8 (2/2 Mon.) ===== | ||
| + | * Interlocking | ||
| + | * Multipath execution | ||
| + | * Fine grain multithreading | ||
| + | * No-op (Bubbles in the pipeline) | ||
| + | * Valid bits in the instructions | ||
| + | * Branch prediction | ||
| + | * Different types of data dependence | ||
| + | * Pipeline stalls | ||
| + | * bubbles | ||
| + | * How to handle stalls | ||
| + | * Stall conditions | ||
| + | * Stall signals | ||
| + | * Dependences | ||
| + | * Distant between dependences | ||
| + | * Data forwarding/bypassing | ||
| + | * Maintaining the correct dataflow | ||
| + | * Different ways to design data forwarding path/logic | ||
| + | * Different techniques to handle interlockings | ||
| + | * SW based | ||
| + | * HW based | ||
| + | * Profiling | ||
| + | * Static profiling | ||
| + | * Helps from the software (compiler) | ||
| + | * Superblock optimization | ||
| + | * Analyzing basic blocks | ||
| + | * How to deal with branches? | ||
| + | * Branch prediction | ||
| + | * Delayed branching (branch delay slot) | ||
| + | * Forward control flow/backward control flow | ||
| + | * Branch prediction accuracy | ||
| + | * Profile guided code positioning | ||
| + | * Based on the profile info. position the code based on it | ||
| + | * Try to make the next sequential instruction be the next inst. to be executed | ||
| + | * Predicate combining (combine predicate for a branch instruction) | ||
| + | * Predicated execution (control dependence becomes data dependence) | ||
| | | ||
| - | | + | |
| + | ===== Lecture 9 (2/4 Wed.) ===== | ||
| + | * Definition of basic blocks | ||
| + | * Control flow graph | ||
| + | * Delayed branching | ||
| + | * benefit? | ||
| + | * What does it eliminates? | ||
| + | * downside? | ||
| + | * Delayed branching in SPARC (with squashing) | ||
| + | * Backward compatibility with the delayed slot | ||
| + | * What should be filled in the delayed slot | ||
| + | * How to ensure correctness | ||
| + | * Fine-grained multithreading | ||
| + | * fetch from different threads | ||
| + | * What are the issues (what if the program doesn't have many threads) | ||
| + | * CDC 6000 | ||
| + | * Denelcor HEP | ||
| + | * No dependency checking | ||
| + | * Inst. from different thread can fill-in the bubbles | ||
| + | * Cost? | ||
| + | * Simulteneuos multithreading | ||
| + | * Branch prediction | ||
| + | * Guess what to fetch next. | ||
| + | * Misprediction penalty | ||
| + | * Need to guess the direction and target | ||
| + | * How to perform the performance analysis? | ||
| + | * Given the branch prediction accuracy and penalty cost, how to compute a cost of a branch misprediction. | ||
| + | * Given the program/number of instructions, percent of branches, branch prediction accuracy and penalty cost, how to compute a cost coming from branch mispredictions. | ||
| + | * How many extra instructions are being fetched? | ||
| + | * What is the performance degredation? | ||
| + | * How to reduce the miss penalty? | ||
| + | * Predicting the next address (non PC+4 address) | ||
| + | * Branch target buffer (BTB) | ||
| + | * Predicting the address of the branch | ||
| + | * Global branch history - for directions | ||
| + | * Can use compiler to profile and get more info | ||
| + | * Input set dictacts the accuracy | ||
| + | * Add time to compilation | ||
| + | * Heuristics that are common and doesn't require profiling. | ||
| + | * Might be inaccurate | ||
| + | * Does not require profiling | ||
| + | * Static branch prediction | ||
| + | * Pregrammer provides pragmas, hinting the likelihood of taken/not taken branch | ||
| + | * For example, x86 has the hint bit | ||
| + | * Dynamic branch prediction | ||
| + | * Last time predictor | ||
| + | * Two bits counter based prediction | ||
| + | * One more bit for hysteresis | ||
| + | ===== Lecture 10 (2/6 Fri.) ===== | ||
| + | * Branch prediction accuracy | ||
| + | * Why are they very important? | ||
| + | * Differences between 99% accuracy and 98% accuracy | ||
| + | * Cost of a misprediction when the pipeline is veryd eep | ||
| + | * Global branch correlation | ||
| + | * Some branches are correlated | ||
| + | * Local branch correlation | ||
| + | * Some branches can depend on the result of past branches | ||
| + | * Pattern history table | ||
| + | * Record global taken/not taken results. | ||
| + | * Cost vs. accuracy (What to record, do you record PC? Just taken/not taken info.?) | ||
| + | * One-level branch predictor | ||
| + | * What information are used | ||
| + | * Two-level branch prediction | ||
| + | * What entries do you keep in the global history? | ||
| + | * What entries do you keep in the local history? | ||
| + | * How many table? | ||
| + | * Cost when training a table | ||
| + | * What are the purposes of each table? | ||
| + | * Potential problems of a two-level history | ||
| + | * GShare predictor | ||
| + | * Global history predictor is hashed with the PC | ||
| + | * Store both GHP and PC in one combined information | ||
| + | * How do you use the information? Why does the XOR result still usable? | ||
| + | * Warmup cost of the branch predictor | ||
| + | * Hybrid solution? Fast warmup is used first, then switch to the slower one. | ||
| + | * Tournament predictor (Alpha 21264) | ||
| + | * Predicated execution - eliminate branches | ||
| + | * What are the tradeoffs | ||
| + | * What if the block is big (can lead to execution a lot of useless work) | ||
| + | * Allows easier code optimization | ||
| + | * From the compiler PoV, predicated execution combine multiple basic blocks into one bigger basic block | ||
| + | * Reduce control dependences | ||
| + | * Need ISA support | ||
| + | * Wish branches | ||
| + | * Compiler generate both predicated and non-predicated codes | ||
| + | * HW design which one to use | ||
| + | * Use branch prediction on an easy to predict code | ||
| + | * Use predicated execution on a hard to predict code | ||
| + | * Compiler can be more aggressive in optimimzing the code | ||
| + | * What are the tradeoffs (slide# 47) | ||
| + | * Multi-path execution | ||
| + | * Execute both paths | ||
| + | * Can lead to wasted work | ||
| + | * VLIW | ||
| + | * SuperScalar | ||
| + | |||
| + | |||
| + | ===== Lecture 11 (2/11 Wed.) ===== | ||
| + | |||
| + | * Geometric GHR length for branch prediction | ||
| + | * Perceptron branch predictor | ||
| + | * Multi-cycle executions (Different functional units take different number of cycles) | ||
| + | * Instructions can retire out-of-order | ||
| + | * How to deal with this case? Stall? Throw exceptions if there are problems? | ||
| + | * Exceptions and Interrupts | ||
| + | * When they are handled? | ||
| + | * Why are some interrupts should be handled right away? | ||
| + | * Precise exception | ||
| + | * arch. state should be consistent before handling the exception/interrupts | ||
| + | * Easier to debug (you see the sequential flow when the interrupt occurs) | ||
| + | * Deterministic | ||
| + | * Easier to recover from the exception | ||
| + | * Easier to restart the processes | ||
| + | * How to ensure precise exception? | ||
| + | * Tradeoffs between each method | ||
| + | * Reorder buffer | ||
| + | * Reorder results before they are visible to the arch. state | ||
| + | * Need to presearve the sequential sematic and data | ||
| + | * What are the informatinos in the ROB entry | ||
| + | * Where to get the value from (forwarding path? reorder buffer?) | ||
| + | * Extra logic to check where the youngest instructions/value is | ||
| + | * Content addressible search (CAM) | ||
| + | * A lot of comparators | ||
| + | * Different ways to simplify the reorder buffer | ||
| + | * Register renaming | ||
| + | * Same register refers to independent values (lacks of registers) | ||
| + | * Where does the exception happen (after retire) | ||
| + | * History buffer | ||
| + | * Update the register file when the instruction complete. Unroll if there is an exception. | ||
| + | * Future file (commonly used, along with reorder buffer) | ||
| + | * Keep two set of register files | ||
| + | * An updated value (Speculative), called future file | ||
| + | * A backup value (to restore the state quickly | ||
| + | * Double the cost of the regfile, but reduce the area as you don't have to use a content addressible memory (compared to ROB alone) | ||
| + | * Branch misprediction resembles Exception | ||
| + | * The difference is that branch misprediction is not visible to the software | ||
| + | * Also much more common (say, divide by zero vs. a mispredicted branch) | ||
| + | * Recovery is similar to exception handling | ||
| + | * Latency of the state recovery | ||
| + | * What to do during the state recovery | ||
| + | * Checkpointing | ||
| + | * Advantages? | ||
| + | |||
| + | ===== Lecture 12 (2/13 Fri.) ===== | ||
| + | |||
| + | * Renaming | ||
| + | * Register renaming table | ||
| + | * Predictor (branch predictor, cache line predictor ...) | ||
| + | * Power budget (and its importance) | ||
| + | * Architectural state, precise state | ||
| + | * Memory dependence is known dynamically | ||
| + | * Register state is not shared across threads/processors | ||
| + | * Memory state is shared across threads/processors | ||
| + | * How to maintain speculative memory states | ||
| + | * Write buffers (helps simplify the process of checking the reorder buffer) | ||
| + | * Overall OoO mechanism | ||
| + | * What are other ways of eliminating dispatch stalls | ||
| + | * Dispatch when the sources are ready | ||
| + | * Retired instructions make the source available | ||
| + | * Register renaming | ||
| + | * Reservation station | ||
| + | * What goes into the reservation station | ||
| + | * Tags required in the reservation station | ||
| + | * Tomasulo's algorithm | ||
| + | * Without precise exception, OoO is hard to debug | ||
| + | * Arch. register ID | ||
| + | * Examples in the slides | ||
| + | * Slides 28 --> register renaming | ||
| + | * Slides 30-35 --> Exercise (also on the board) | ||
| + | * This will be usefull for the midterm | ||
| + | * Register aliasing table | ||
| + | * Broadcasting tags | ||
| + | * Using dataflow | ||
| + | |||
| + | |||
| + | ===== Lecture 13 (2/16 Mon.) ===== | ||
| + | |||
| + | * OoO --> Restricted Dataflow | ||
| + | * Extracting parallelism | ||
| + | * What are the bottlenecks? | ||
| + | * Issue width | ||
| + | * Dispatch width | ||
| + | * Parallelism in the program | ||
| + | * What does it mean to be restricted data flow | ||
| + | * Still visible as a Von Neumann model | ||
| + | * Where does the efficiency come from? | ||
| + | * Size of the scheduling windors/reorder buffer. Tradeoffs? What make sense? | ||
| + | * Load/store handling | ||
| + | * Would like to schedule them out of order, but make them visible in-order | ||
| + | * When do you schedule the load/store instructions? | ||
| + | * Can we predict if load/store are dependent? | ||
| + | * This is one of the most complex structure of the load/store handling | ||
| + | * What information can be used to predict these load/store optimization? | ||
| + | * Centralized vs. distributed? What are the tradeoffs? | ||
| + | * How to handle when there is a misprediction/recovery | ||
| + | * OoO + branch prediction? | ||
| + | * Speculatively update the history register | ||
| + | * When do you update the GHR? | ||
| + | * Token dataflow arch. | ||
| + | * What are tokens? | ||
| + | * How to match tokens | ||
| + | * Tagged token dataflow arch. | ||
| + | * What are the tradeoffs? | ||
| + | * Difficulties? | ||
| + | |||
| + | ===== Lecture 14 (2/18 Wed.) ===== | ||
| + | |||
| + | * SISD/SIMD/MISD/MIMD | ||
| + | * Array processor | ||
| + | * Vector processor | ||
| + | * Data parallelism | ||
| + | * Where does the concurrency arise? | ||
| + | * Differences between array processor vs. vector processor | ||
| + | * VLIW | ||
| + | * Compactness of an array processor | ||
| + | * Vector operates on a vector of data (rather than a single datum (scalar)) | ||
| + | * Vector length (also applies to array processor) | ||
| + | * No dependency within a vector --> can have a deep pipeline | ||
| + | * Highly parallel (both instruction level (ILP) and memory level (MLP)) | ||
| + | * But the program needs to be very parallel | ||
| + | * Memory can be the bottleneck (due to very high MLP) | ||
| + | * What does the functional units look like? Deep pipelin and simpler control. | ||
| + | * CRAY-I is one of the examples of vector processor | ||
| + | * Memory access pattern in a vector processor | ||
| + | * How do the memory accesses benefit the memory bandwidth? | ||
| + | * Memory level parallelism | ||
| + | * Stride length vs. the number of banks | ||
| + | * stride length should be relatively prime to the number of banks | ||
| + | * Tradeoffs between row major and column major --> How can the vector processor deals with the two | ||
| + | * How to calculate the efficiency and performance of vector processors | ||
| + | * What if there are multiple memory ports? | ||
| + | * Gather/Scatter allows vector processor to be a lot more programmable (i.e. gather data for parallelism) | ||
| + | * Helps handling sparse metrices | ||
| + | * Conditional operation | ||
| + | * Structure of vector units | ||
| + | * How to automatically parallelize code through the compiler? | ||
| + | * This is a hard problem. Compiler does not know the memory address. | ||
| + | * What do we need to ensure for both vector and array processor? | ||
| + | * Sequential bottleneck | ||
| + | * Amdahl's law | ||
| + | * Intel MMX --> An example of Intel's approach to SIMD | ||
| + | * No VLEN, use OpCode to define the length | ||
| + | * Stride is one in MMX | ||
| + | * Intel SSE --> Modern version of MMX | ||
| + | |||
| + | ===== Lecture 15 (2/20 Fri.) ===== | ||
| + | * GPU | ||
| + | * Warp/Wavefront | ||
| + | * A bunch of threads sharing the same PC | ||
| + | * SIMT | ||
| + | * Lanes | ||
| + | * FGMT + massively parallel | ||
| + | * Tolerate long latency | ||
| + | * Warp based SIMD vs. traditional SIMD | ||
| + | * SPMD (Programming model) | ||
| + | * Single program operates on multiple data | ||
| + | * can have synchronization point | ||
| + | * Many scientific applications are programmed in this manner | ||
| + | * Control flow problem (branch divergence) | ||
| + | * Masking (in a branch, mask threads that should not execute that path) | ||
| + | * Lower SIMD efficiency | ||
| + | * What if you have layers of branches? | ||
| + | * Dynamic wrap formation | ||
| + | * Combining threads from different warps to increase SIMD utilization | ||
| + | * This can cause memory divergence | ||
| + | * VLIW | ||
| + | * Wide fetch | ||
| + | * IA-64 | ||
| + | * Tradeoffs | ||
| + | * Simple hardware (no dynamic scheduling, no dependency checking within VLIW) | ||
| + | * A lot of loads at the compiler level | ||
| + | * Decoupled access/execute | ||
| + | * Limited form of OoO | ||
| + | * Tradeoffs | ||
| + | * How to street the instruction (determine dependency/stalling)? | ||
| + | * Instruction scheduling techniques (static vs. dynamic) | ||
| + | * Systoric arrays | ||
| + | * Processing elements transform data in chains | ||
| + | * Develop for image processing (for example, convolution) | ||
| + | * Stage processing | ||
| | | ||
| + | |||
| + | |||
| + | ===== Lecture 16 (2/23 Mon.) ===== | ||
| + | * Systoric arrays | ||
| + | * Processing elements transform data in chains | ||
| + | * Can be arrays of multi-dimensional processing elements | ||
| + | * Develop for image processing (for example, convolution) | ||
| + | * Can be use to break stages in pipeline programs, using a set of queues and processing elements | ||
| + | * Can enable high concurrency and good for regular programs | ||
| + | * Very special purpose | ||
| + | * The warp computer | ||
| + | * Static instruction scheduling | ||
| + | * How do we find the next instruction to execute? | ||
| + | * Live-in and live-out | ||
| + | * Basic blocks | ||
| + | * Rearranging instructions in the basic block | ||
| + | * Code movement from one basic block to another | ||
| + | * Straight line code | ||
| + | * Independent instructions | ||
| + | * How to identify independent instructions | ||
| + | * Atomicity | ||
| + | * Trace scheduling | ||
| + | * Side entrance | ||
| + | * Fixed up code | ||
| + | * How scheudling is done | ||
| + | * Instruction scheduling | ||
| + | * Prioritization heuristics | ||
| + | * Superblock | ||
| + | * Traces with no side-entrance | ||
| + | * Hyperblock | ||
| + | * BS-ISA | ||
| + | * Tradeoffs betwwen trace cache/Hyperblock/Superblock/BS-ISA | ||
| + | | ||
| + | |||
| + | * IA-64 | ||
| + | * EPIC | ||
| + | * IA-64 instruction bundle | ||
| + | * Multiple instructions in the bundle along with the template bit | ||
| + | * Template bits | ||
| + | * Stop bits | ||
| + | * Non-faulting loads and exception propagation | ||
| + | * Aggressive ST-LD reordering | ||
| + | * Phyiscal memory system | ||
| + | * Ideal pipelines | ||
| + | * Ideal cache | ||
| + | * More capacity | ||
| + | * Fast | ||
| + | * Cheap | ||
| + | * High bandwidth | ||
| + | * DRAM cell | ||
| + | * Cheap | ||
| + | * Sense the purturbation through sense amplifier | ||
| + | * Slow and leaky | ||
| + | * SRAM cell (Cross coupled inverter) | ||
| + | * Expensice | ||
| + | * Fast (easier to sense the value in the cell) | ||
| + | * Memory bank | ||
| + | * Read access sequence | ||
| + | * DRAM: Activate -> Read -> Precharge (if needed) | ||
| + | * What dominate the access laatency for DRAM and SRAM | ||
| + | * Scaling issue | ||
| + | * Hard to scale the scale to be small | ||
| + | * Memory hierarchy | ||
| + | * Prefetching | ||
| + | * Caching | ||
| + | * Spatial and temporal locality | ||
| + | * Cache can exploit these | ||
| + | * Recently used data is likely to be accessed | ||
| + | * Nearby data is likely to be accessed | ||
| + | * Caching in a pipeline design | ||
| + | * Cache management | ||
| + | * Manual | ||
| + | * Data movement is managed manually | ||
| + | * Embedded processor | ||
| + | * GPU scratchpad | ||
| + | * Automatic | ||
| + | * HW manage data movements | ||
| + | * Latency analysis | ||
| + | * Based on the hit and miss status, next level access time (if miss), and the current level access time | ||
| + | * Cache basics | ||
| + | * Set/block (line)/Placement/replacement/direct mapped vs. associative cache/etc. | ||
| + | * Cache access | ||
| + | * How to access tag and data (in parallel vs serially) | ||
| + | * How do tag and index get used? | ||
| + | * Modern processors perform serial access for higher level cache (L3 for example) to save power | ||
| + | * Cost and benefit of having more associativity | ||
| + | * Given the associativity, which block should be replace if it is full | ||
| + | * Replacement poligy | ||
| + | * Random | ||
| + | * Least recently used (LRU) | ||
| + | * Least frequently used | ||
| + | * Least costly to refetch | ||
| + | * etc. | ||
| + | * How to implement LRU | ||
| + | * How to keep track of access ordering | ||
| + | * Complexity increases rapidly | ||
| + | * Approximate LRU | ||
| + | * Victim and next Victim policy | ||
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
Page Tools
Except where otherwise noted, content on this wiki is licensed under the following license: CC Attribution-Share Alike 3.0 Unported
