buzzword
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buzzword [2015/01/30 19:24] rachata |
buzzword [2015/02/04 19:24] rachata |
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| * Primitives | * Primitives | ||
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| - | ===== Lecture 7 (1/30 Mon.) ===== | + | ===== Lecture 7 (1/30 Fri.) ===== |
| * Emulator (i.e. uCode allots minimal datapath to emulate the ISA) | * Emulator (i.e. uCode allots minimal datapath to emulate the ISA) | ||
| Line 277: | Line 277: | ||
| * Pipeline flush | * Pipeline flush | ||
| * Speculation | * Speculation | ||
| - | |||
| - | | ||
| | | ||
| + | ===== Lecture 8 (2/2 Mon.) ===== | ||
| + | * Interlocking | ||
| + | * Multipath execution | ||
| + | * Fine grain multithreading | ||
| + | * No-op (Bubbles in the pipeline) | ||
| + | * Valid bits in the instructions | ||
| + | * Branch prediction | ||
| + | * Different types of data dependence | ||
| + | * Pipeline stalls | ||
| + | * bubbles | ||
| + | * How to handle stalls | ||
| + | * Stall conditions | ||
| + | * Stall signals | ||
| + | * Dependences | ||
| + | * Distant between dependences | ||
| + | * Data forwarding/bypassing | ||
| + | * Maintaining the correct dataflow | ||
| + | * Different ways to design data forwarding path/logic | ||
| + | * Different techniques to handle interlockings | ||
| + | * SW based | ||
| + | * HW based | ||
| + | * Profiling | ||
| + | * Static profiling | ||
| + | * Helps from the software (compiler) | ||
| + | * Superblock optimization | ||
| + | * Analyzing basic blocks | ||
| + | * How to deal with branches? | ||
| + | * Branch prediction | ||
| + | * Delayed branching (branch delay slot) | ||
| + | * Forward control flow/backward control flow | ||
| + | * Branch prediction accuracy | ||
| + | * Profile guided code positioning | ||
| + | * Based on the profile info. position the code based on it | ||
| + | * Try to make the next sequential instruction be the next inst. to be executed | ||
| + | * Predicate combining (combine predicate for a branch instruction) | ||
| + | * Predicated execution (control dependence becomes data dependence) | ||
| + | | ||
| | | ||
| + | ===== Lecture 9 (2/4 Wed.) ===== | ||
| + | * Definition of basic blocks | ||
| + | * Control flow graph | ||
| + | * Delayed branching | ||
| + | * benefit? | ||
| + | * What does it eliminates? | ||
| + | * downside? | ||
| + | * Delayed branching in SPARC (with squashing) | ||
| + | * Backward compatibility with the delayed slot | ||
| + | * What should be filled in the delayed slot | ||
| + | * How to ensure correctness | ||
| + | * Fine-grained multithreading | ||
| + | * fetch from different threads | ||
| + | * What are the issues (what if the program doesn't have many threads) | ||
| + | * CDC 6000 | ||
| + | * Denelcor HEP | ||
| + | * No dependency checking | ||
| + | * Inst. from different thread can fill-in the bubbles | ||
| + | * Cost? | ||
| + | * Simulteneuos multithreading | ||
| + | * Branch prediction | ||
| + | * Guess what to fetch next. | ||
| + | * Misprediction penalty | ||
| + | * Need to guess the direction and target | ||
| + | * How to perform the performance analysis? | ||
| + | * Given the branch prediction accuracy and penalty cost, how to compute a cost of a branch misprediction. | ||
| + | * Given the program/number of instructions, percent of branches, branch prediction accuracy and penalty cost, how to compute a cost coming from branch mispredictions. | ||
| + | * How many extra instructions are being fetched? | ||
| + | * What is the performance degredation? | ||
| + | * How to reduce the miss penalty? | ||
| + | * Predicting the next address (non PC+4 address) | ||
| + | * Branch target buffer (BTB) | ||
| + | * Predicting the address of the branch | ||
| + | * Global branch history - for directions | ||
| + | * Can use compiler to profile and get more info | ||
| + | * Input set dictacts the accuracy | ||
| + | * Add time to compilation | ||
| + | * Heuristics that are common and doesn't require profiling. | ||
| + | * Might be inaccurate | ||
| + | * Does not require profiling | ||
| + | * Static branch prediction | ||
| + | * Pregrammer provides pragmas, hinting the likelihood of taken/not taken branch | ||
| + | * For example, x86 has the hint bit | ||
| + | * Dynamic branch prediction | ||
| + | * Last time predictor | ||
| + | * Two bits counter based prediction | ||
| + | * One more bit for hysteresis | ||
| + | |||
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
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