buzzword
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buzzword [2015/01/16 19:44] kevincha |
buzzword [2015/01/26 23:13] kevincha [Lecture 4 (1/21 Wed.)] |
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| ===== Lecture 3 (1/17 Fri.) ===== | ===== Lecture 3 (1/17 Fri.) ===== | ||
| - | * Microarchitecture | + | * Microarchitecture |
| + | * Three major tradeoffs of computer architecture | ||
| + | * Macro-architecture | ||
| + | * LC-3b ISA | ||
| + | * Unused instructions | ||
| + | * Bit steering | ||
| + | * Instruction processing style | ||
| + | * 0,1,2,3 address machines | ||
| + | * Stack machine | ||
| + | * Accumulator machine | ||
| + | * 2-operand machine | ||
| + | * 3-operand machine | ||
| + | * Tradeoffs between 0,1,2,3 address machines | ||
| + | * Postfix notation | ||
| + | * Instructions/Opcode/Operade specifiers (i.e. addressing modes) | ||
| + | * Simply vs. complex data type (and their tradeoffs) | ||
| + | * Semantic gap and level | ||
| + | * Translation layer | ||
| + | * Addressability | ||
| + | * Byte/bit addressable machines | ||
| + | * Virtual memory | ||
| + | * Big/little endian | ||
| + | * Benefits of having registers (data locality) | ||
| + | * Programmer visible (Architectural) state | ||
| + | * Programmers can access this directly | ||
| + | * What are the benefits? | ||
| + | * Microarchitectural state | ||
| + | * Programmers cannot access this directly | ||
| + | * Evolution of registers (from accumulators to registers) | ||
| + | * Different types of instructions | ||
| + | * Control instructions | ||
| + | * Data instructions | ||
| + | * Operation instructions | ||
| + | * Addressing modes | ||
| + | * Tradeoffs (complexity, flexibility, etc.) | ||
| + | * Orthogonal ISA | ||
| + | * Addressing modes that are orthogonal to instruction types | ||
| + | * I/O devices | ||
| + | * Vectored vs. non-vectored interrupts | ||
| + | * Complex vs. simple instructions | ||
| + | * Tradeoffs | ||
| + | * RISC vs. CISC | ||
| + | * Tradeoff | ||
| + | * Backward compatibility | ||
| + | * Performance | ||
| + | * Optimization opportunity | ||
| + | * Translation | ||
| - | * Three major tradeoffs of computer architecture | + | ===== Lecture 4 (1/21 Wed.) ===== |
| - | * Macro-architecture | + | * Fixed vs. variable length instruction |
| + | * Huffman encoding | ||
| + | * Uniform vs. non-uniform decode | ||
| + | * Registers | ||
| + | * Tradeoffs between number of registers | ||
| + | * Alignments | ||
| + | * How does MIPS load words across alignment the boundary | ||
| - | * LC-3b ISA | + | ===== Lecture 5 (1/26 Mon.) ===== |
| - | * Unused instructions | + | * Tradeoffs in ISA: Instruction length |
| - | + | * Uniform vs. non-uniform | |
| - | * Bit steering | + | * Design point/Use cases |
| - | + | * What dictates the design point? | |
| - | * Instruction processing style | + | * Architectural states |
| - | + | * uArch | |
| - | * 0,1,2,3 address machines | + | * How to implement the ISA in the uArch |
| - | + | * Different stages in the uArch | |
| - | * Stack machine | + | * Clock cycles |
| - | + | * Multi-cycle machine | |
| - | * Accumulator machine | + | * Datapath and control logic |
| - | + | * Control signals | |
| - | * 2-operand machine | + | * Execution time of instructions/program |
| - | + | * Metrics and what do they means | |
| - | * 3-operand machine | + | * Instruction processing |
| - | + | * Fetch | |
| - | * Tradeoffs between 0,1,2,3 address machines | + | * Decode |
| - | + | * Execute | |
| - | * Postfix notation | + | * Memory fetch |
| - | + | * Writeback | |
| - | * Instructions/Opcode/Operade specifiers (i.e. addressing modes) | + | * Encoding and semantics |
| - | + | * Different types of instructions (I-type, R-type, etc.) | |
| - | * Simply vs. complex data type (and their tradeoffs) | + | * Control flow instructions |
| - | + | * Non-control flow instructions | |
| - | * Semantic gap and level | + | * Delayed slot/Delayed branch |
| - | + | * Single cycle control logic | |
| - | * Translation layer | + | * Lockstep |
| - | + | * Critical path analysis | |
| - | * Addressability | + | * Critical path of a single cycle processor |
| - | + | * What is in the control signals? | |
| - | * Byte/bit addressable machines | + | * Combinational logic & Sequential logic |
| - | + | * Control store | |
| - | * Virtual memory | + | * Tradeoffs of a single cycle uarch |
| - | + | * Design principles | |
| - | * Big/little endian | + | * Common case design |
| - | + | * Critical path design | |
| - | * Benefits of having registers (data locality) | + | * Balanced designs |
| - | + | * Dynamic power/Static power | |
| - | * Programmer visible (Architectural) state | + | * Increases in power due to frequency |
| - | + | ||
| - | * Programmers can access this directly | + | |
| - | + | ||
| - | * What are the benefits? | + | |
| - | + | ||
| - | * Microarchitectural state | + | |
| - | + | ||
| - | * Programmers cannot access this directly | + | |
| - | + | ||
| - | * Evolution of registers (from accumulators to registers) | + | |
| - | + | ||
| - | * Different types of instructions | + | |
| - | + | ||
| - | * Control instructions | + | |
| - | + | ||
| - | * Data instructions | + | |
| - | + | ||
| - | * Operation instructions | + | |
| - | + | ||
| - | * Addressing modes | + | |
| - | + | ||
| - | * Tradeoffs (complexity, flexibility, etc.) | + | |
| - | + | ||
| - | * Orthogonal ISA | + | |
| - | + | ||
| - | * Addressing modes that are orthogonal to instruction types | + | |
| - | + | ||
| - | * I/O devices | + | |
| - | + | ||
| - | * Vectored vs. non-vectored interrupts | + | |
| - | + | ||
| - | * Complex vs. simple instructions | + | |
| - | + | ||
| - | * Tradeoffs | + | |
| - | + | ||
| - | * RISC vs. CISC | + | |
| - | + | ||
| - | * Tradeoff | + | |
| - | + | ||
| - | * Backward compatibility | + | |
| - | + | ||
| - | * Performance | + | |
| - | + | ||
| - | * Optimization opportunity | + | |
| - | + | ||
| - | * Translation | + | |
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
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