buzzword
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buzzword [2015/01/14 19:44] rachata |
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| * DIfferent types of data flow nodes (conditional/relational/barrier) | * DIfferent types of data flow nodes (conditional/relational/barrier) | ||
| * How to do transactional transaction in dataflow? | * How to do transactional transaction in dataflow? | ||
| - | Example: bank transactions | + | * Example: bank transactions |
| * Tradeoffs between control-driven and data-driven | * Tradeoffs between control-driven and data-driven | ||
| * What are easier to program? | * What are easier to program? | ||
| Line 104: | Line 104: | ||
| * What are not a part of the ISA? (what goes inside: uArch techniques) | * What are not a part of the ISA? (what goes inside: uArch techniques) | ||
| * Things that are not suppose to be visible to the programmer/software but typically make the processor faster and/or consumes less power and/or less complex | * Things that are not suppose to be visible to the programmer/software but typically make the processor faster and/or consumes less power and/or less complex | ||
| + | |||
| + | ===== Lecture 3 (1/17 Fri.) ===== | ||
| + | |||
| + | * Microarchitecture | ||
| + | * Three major tradeoffs of computer architecture | ||
| + | * Macro-architecture | ||
| + | * LC-3b ISA | ||
| + | * Unused instructions | ||
| + | * Bit steering | ||
| + | * Instruction processing style | ||
| + | * 0,1,2,3 address machines | ||
| + | * Stack machine | ||
| + | * Accumulator machine | ||
| + | * 2-operand machine | ||
| + | * 3-operand machine | ||
| + | * Tradeoffs between 0,1,2,3 address machines | ||
| + | * Postfix notation | ||
| + | * Instructions/Opcode/Operade specifiers (i.e. addressing modes) | ||
| + | * Simply vs. complex data type (and their tradeoffs) | ||
| + | * Semantic gap and level | ||
| + | * Translation layer | ||
| + | * Addressability | ||
| + | * Byte/bit addressable machines | ||
| + | * Virtual memory | ||
| + | * Big/little endian | ||
| + | * Benefits of having registers (data locality) | ||
| + | * Programmer visible (Architectural) state | ||
| + | * Programmers can access this directly | ||
| + | * What are the benefits? | ||
| + | * Microarchitectural state | ||
| + | * Programmers cannot access this directly | ||
| + | * Evolution of registers (from accumulators to registers) | ||
| + | * Different types of instructions | ||
| + | * Control instructions | ||
| + | * Data instructions | ||
| + | * Operation instructions | ||
| + | * Addressing modes | ||
| + | * Tradeoffs (complexity, flexibility, etc.) | ||
| + | * Orthogonal ISA | ||
| + | * Addressing modes that are orthogonal to instruction types | ||
| + | * I/O devices | ||
| + | * Vectored vs. non-vectored interrupts | ||
| + | * Complex vs. simple instructions | ||
| + | * Tradeoffs | ||
| + | * RISC vs. CISC | ||
| + | * Tradeoff | ||
| + | * Backward compatibility | ||
| + | * Performance | ||
| + | * Optimization opportunity | ||
| + | * Translation | ||
| + | |||
| + | ===== Lecture 4 (1/21 Wed.) ===== | ||
| + | |||
| + | * Fixed vs. variable length instruction | ||
| + | * Huffman encoding | ||
| + | * Uniform vs. non-uniform decode | ||
| + | * Registers | ||
| + | * Tradeoffs between number of registers | ||
| + | * Alignments | ||
| + | * How does MIPS load words across alignment the boundary | ||
| + | |||
| + | ===== Lecture 5 (1/26 Mon.) ===== | ||
| + | |||
| + | * Tradeoffs in ISA: Instruction length | ||
| + | * Uniform vs. non-uniform | ||
| + | * Design point/Use cases | ||
| + | * What dictates the design point? | ||
| + | * Architectural states | ||
| + | * uArch | ||
| + | * How to implement the ISA in the uArch | ||
| + | * Different stages in the uArch | ||
| + | * Clock cycles | ||
| + | * Multi-cycle machine | ||
| + | * Datapath and control logic | ||
| + | * Control signals | ||
| + | * Execution time of instructions/program | ||
| + | * Metrics and what do they means | ||
| + | * Instruction processing | ||
| + | * Fetch | ||
| + | * Decode | ||
| + | * Execute | ||
| + | * Memory fetch | ||
| + | * Writeback | ||
| + | * Encoding and semantics | ||
| + | * Different types of instructions (I-type, R-type, etc.) | ||
| + | * Control flow instructions | ||
| + | * Non-control flow instructions | ||
| + | * Delayed slot/Delayed branch | ||
| + | * Single cycle control logic | ||
| + | * Lockstep | ||
| + | * Critical path analysis | ||
| + | * Critical path of a single cycle processor | ||
| + | * What is in the control signals? | ||
| + | * Combinational logic & Sequential logic | ||
| + | * Control store | ||
| + | * Tradeoffs of a single cycle uarch | ||
| + | * Design principles | ||
| + | * Common case design | ||
| + | * Critical path design | ||
| + | * Balanced designs | ||
| + | * Dynamic power/Static power | ||
| + | * Increases in power due to frequency | ||
| + | |||
| + | ===== Lecture 6 (1/28 Mon.) ===== | ||
| + | |||
| + | * Design principles | ||
| + | * Common case design | ||
| + | * Critical path design | ||
| + | * Balanced designs | ||
| + | * Multi cycle design | ||
| + | * Microcoded/Microprogrammed machines | ||
| + | * States | ||
| + | * Translation from one state to another | ||
| + | * Microinstructions | ||
| + | * Microsequencing | ||
| + | * Control store - Product control signals | ||
| + | * Microsequencer | ||
| + | * Control signal | ||
| + | * What do they have to control? | ||
| + | * Instruction processing cycle | ||
| + | * Latch signals | ||
| + | * State machine | ||
| + | * State variables | ||
| + | * Condition code | ||
| + | * Steering bits | ||
| + | * Branch enable logic | ||
| + | * Difference between gating and loading? (write enable vs. driving the bus) | ||
| + | * Memory mapped I/O | ||
| + | * Hardwired logic | ||
| + | * What control signals come from hardwired logic? | ||
| + | * Variable latency memory | ||
| + | * Handling interrupts | ||
| + | * Difference betwen interrupts and exceptions | ||
| + | * Emulator (i.e. uCode allots minimal datapath to emulate the ISA) | ||
| + | * Updating machine behavior | ||
| + | * Horizontal microcode | ||
| + | * Vertical microcode | ||
| + | * Primitives | ||
| + | | ||
| + | |||
| + | | ||
buzzword.txt · Last modified: 2015/04/27 18:20 by rachata
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