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buzzword [2015/01/13 01:37] kevincha [Lecture 1 (1/12 Mon.)] |
buzzword [2015/01/26 23:13] kevincha [Lecture 4 (1/21 Wed.)] |
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* Compiler | * Compiler | ||
* Cross abstraction layers | * Cross abstraction layers | ||
- | * Exposing an interface | ||
* Tradeoffs | * Tradeoffs | ||
* Caches | * Caches | ||
- | * Multi-thread | ||
- | * Multi-core | ||
- | * Unfairness | ||
* DRAM/memory controller | * DRAM/memory controller | ||
- | * Memory hog | + | * DRAM banks |
* Row buffer hit/miss | * Row buffer hit/miss | ||
* Row buffer locality | * Row buffer locality | ||
- | * Streaming access vs. random access | + | * Unfairness |
- | * Power consumption | + | |
- | * Bloom filter | + | |
- | * Memory performance attacks | + | |
- | * Hamming code | + | |
- | * Hamming distance | + | |
- | * Abstraction layer | + | |
* Memory performance hog | * Memory performance hog | ||
* Shared DRAM memory system | * Shared DRAM memory system | ||
- | * Unfairness | + | * Streaming access vs. random access |
- | * DRAM banks | + | |
* Memory scheduling policies | * Memory scheduling policies | ||
* Scheduling priority | * Scheduling priority | ||
Line 35: | Line 24: | ||
* Process variation | * Process variation | ||
* Retention time profile | * Retention time profile | ||
+ | * Power consumption | ||
+ | * Bloom filter | ||
+ | * Hamming code | ||
+ | * Hamming distance | ||
* DRAM row hammer | * DRAM row hammer | ||
+ | ===== Lecture 2 (1/14 Wed.) ===== | ||
+ | * Moore's Law | ||
+ | * Algorithm --> step-by-step procedure to solve a problem | ||
+ | * in-order execution | ||
+ | * out-of-order execution | ||
+ | * technologies that are available on cellphones | ||
+ | * new applications that are made available through new computer architecture techniques | ||
+ | * more data mining (genomics/medical areas) | ||
+ | * lower power (cellphones) | ||
+ | * smaller cores (cellphones/computers) | ||
+ | * etc. | ||
+ | * Performance bottlenecks in a single thread/core processors | ||
+ | * multi-core as an alternative | ||
+ | * Memory wall (a part of scaling issue) | ||
+ | * Scaling issue | ||
+ | * Transister are getting smaller | ||
+ | * Key components of a computer | ||
+ | * Design points | ||
+ | * Design processors to meet the design points | ||
+ | * Software stack | ||
+ | * Design decisions | ||
+ | * Datacenters | ||
+ | * Reliability problems that cause errors | ||
+ | * Analogies from Kuhn's "The Structure of Scientific Revolutions" (Recommended book) | ||
+ | * Pre paradigm science | ||
+ | * Normal science | ||
+ | * Revolutionalry science | ||
+ | * Components of a computer | ||
+ | * Computation | ||
+ | * Communication | ||
+ | * Storage | ||
+ | * DRAM | ||
+ | * NVRAM (Non-volatile memory): PCM, STT-MRAM | ||
+ | * Storage (Flash/Harddrive) | ||
+ | * Von Neumann Model (Control flow model) | ||
+ | * Stored program computer | ||
+ | * Properties of Von Neumann Model: Stored program, sequential instruction processing | ||
+ | * Unified memory | ||
+ | * When does an instruction is being interpreted as an instruction (as oppose to a datum)? | ||
+ | * Program counter | ||
+ | * Examples: x86, ARM, Alpha, IBM Power series, SPARC, MIPS | ||
+ | * Data flow model | ||
+ | * Data flow machine | ||
+ | * Data flow graph | ||
+ | * Operands | ||
+ | * Live-outs/Live-ins | ||
+ | * DIfferent types of data flow nodes (conditional/relational/barrier) | ||
+ | * How to do transactional transaction in dataflow? | ||
+ | * Example: bank transactions | ||
+ | * Tradeoffs between control-driven and data-driven | ||
+ | * What are easier to program? | ||
+ | * Which are easy to compile? | ||
+ | * What are more parallel (does that mean it is faster?) | ||
+ | * Which machines are more complex to design? | ||
+ | * In control flow, when a program is stop, there is a pointer to the current state (precise state). | ||
+ | * ISA vs. Microarchitecture | ||
+ | * Semantics in the ISA | ||
+ | * uArch should obey the ISA | ||
+ | * Changing ISA is costly, can affect compatibility. | ||
+ | * Instruction pointers | ||
+ | * uArch techniques: common and powerful techniques break Vonn Neumann model if done at the ISA level | ||
+ | * Conceptual techniques | ||
+ | * Pipelining | ||
+ | * Multiple instructions at a time | ||
+ | * Out-of-order executions | ||
+ | * etc. | ||
+ | * Design techniques | ||
+ | * Adder implementation (Bit serial, ripple carry, carry lookahead) | ||
+ | * Connection machine (an example of a machine that use bit serial to tradeoff latency for more parallelism) | ||
+ | * Microprocessor: ISA + uArch + circuits | ||
+ | * What are a part of the ISA? Instructions, memory, etc. | ||
+ | * Things that are visible to the programmer/software | ||
+ | * What are not a part of the ISA? (what goes inside: uArch techniques) | ||
+ | * Things that are not suppose to be visible to the programmer/software but typically make the processor faster and/or consumes less power and/or less complex | ||
+ | |||
+ | ===== Lecture 3 (1/17 Fri.) ===== | ||
+ | |||
+ | * Microarchitecture | ||
+ | * Three major tradeoffs of computer architecture | ||
+ | * Macro-architecture | ||
+ | * LC-3b ISA | ||
+ | * Unused instructions | ||
+ | * Bit steering | ||
+ | * Instruction processing style | ||
+ | * 0,1,2,3 address machines | ||
+ | * Stack machine | ||
+ | * Accumulator machine | ||
+ | * 2-operand machine | ||
+ | * 3-operand machine | ||
+ | * Tradeoffs between 0,1,2,3 address machines | ||
+ | * Postfix notation | ||
+ | * Instructions/Opcode/Operade specifiers (i.e. addressing modes) | ||
+ | * Simply vs. complex data type (and their tradeoffs) | ||
+ | * Semantic gap and level | ||
+ | * Translation layer | ||
+ | * Addressability | ||
+ | * Byte/bit addressable machines | ||
+ | * Virtual memory | ||
+ | * Big/little endian | ||
+ | * Benefits of having registers (data locality) | ||
+ | * Programmer visible (Architectural) state | ||
+ | * Programmers can access this directly | ||
+ | * What are the benefits? | ||
+ | * Microarchitectural state | ||
+ | * Programmers cannot access this directly | ||
+ | * Evolution of registers (from accumulators to registers) | ||
+ | * Different types of instructions | ||
+ | * Control instructions | ||
+ | * Data instructions | ||
+ | * Operation instructions | ||
+ | * Addressing modes | ||
+ | * Tradeoffs (complexity, flexibility, etc.) | ||
+ | * Orthogonal ISA | ||
+ | * Addressing modes that are orthogonal to instruction types | ||
+ | * I/O devices | ||
+ | * Vectored vs. non-vectored interrupts | ||
+ | * Complex vs. simple instructions | ||
+ | * Tradeoffs | ||
+ | * RISC vs. CISC | ||
+ | * Tradeoff | ||
+ | * Backward compatibility | ||
+ | * Performance | ||
+ | * Optimization opportunity | ||
+ | * Translation | ||
+ | |||
+ | ===== Lecture 4 (1/21 Wed.) ===== | ||
+ | |||
+ | * Fixed vs. variable length instruction | ||
+ | * Huffman encoding | ||
+ | * Uniform vs. non-uniform decode | ||
+ | * Registers | ||
+ | * Tradeoffs between number of registers | ||
+ | * Alignments | ||
+ | * How does MIPS load words across alignment the boundary | ||
+ | |||
+ | ===== Lecture 5 (1/26 Mon.) ===== | ||
+ | |||
+ | * Tradeoffs in ISA: Instruction length | ||
+ | * Uniform vs. non-uniform | ||
+ | * Design point/Use cases | ||
+ | * What dictates the design point? | ||
+ | * Architectural states | ||
+ | * uArch | ||
+ | * How to implement the ISA in the uArch | ||
+ | * Different stages in the uArch | ||
+ | * Clock cycles | ||
+ | * Multi-cycle machine | ||
+ | * Datapath and control logic | ||
+ | * Control signals | ||
+ | * Execution time of instructions/program | ||
+ | * Metrics and what do they means | ||
+ | * Instruction processing | ||
+ | * Fetch | ||
+ | * Decode | ||
+ | * Execute | ||
+ | * Memory fetch | ||
+ | * Writeback | ||
+ | * Encoding and semantics | ||
+ | * Different types of instructions (I-type, R-type, etc.) | ||
+ | * Control flow instructions | ||
+ | * Non-control flow instructions | ||
+ | * Delayed slot/Delayed branch | ||
+ | * Single cycle control logic | ||
+ | * Lockstep | ||
+ | * Critical path analysis | ||
+ | * Critical path of a single cycle processor | ||
+ | * What is in the control signals? | ||
+ | * Combinational logic & Sequential logic | ||
+ | * Control store | ||
+ | * Tradeoffs of a single cycle uarch | ||
+ | * Design principles | ||
+ | * Common case design | ||
+ | * Critical path design | ||
+ | * Balanced designs | ||
+ | * Dynamic power/Static power | ||
+ | * Increases in power due to frequency | ||
+ | |